system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC =  E12;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC = T15;
Net sys_rst_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin PULLDOWN;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
Net sys_rst_pin TIG;

## IO Devices constraints

#### PS/2 Mouse and Keyboard

# Primary connection
NET "plb_ps2_controller_0_mouse_clk_pin" LOC = "W12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "plb_ps2_controller_0_mouse_data_pin" LOC = "V11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
# Secondary connection (requires Y-splitter cable)
NET "plb_ps2_controller_0_key_clk_pin" LOC = "U11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "plb_ps2_controller_0_key_data_pin" LOC = "Y12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;



#### VGA CONNECTOR

Net tft_lcd_hsync LOC = C11 | IOSTANDARD = LVCMOS33;
Net tft_lcd_vsync LOC = B11 | IOSTANDARD = LVCMOS33;
Net tft_lcd_r<2> LOC = A3 | IOSTANDARD = LVCMOS33;
Net tft_lcd_r<3> LOC = B3 | IOSTANDARD = LVCMOS33;
Net tft_lcd_r<4> LOC = B8 | IOSTANDARD = LVCMOS33;
Net tft_lcd_r<5> LOC = C8 | IOSTANDARD = LVCMOS33;
Net tft_lcd_g<2> LOC = C5 | IOSTANDARD = LVCMOS33;
Net tft_lcd_g<3> LOC = D5 | IOSTANDARD = LVCMOS33;
Net tft_lcd_g<4> LOC = C6 | IOSTANDARD = LVCMOS33;
Net tft_lcd_g<5> LOC = D6 | IOSTANDARD = LVCMOS33;
Net tft_lcd_b<2> LOC = C7 | IOSTANDARD = LVCMOS33;
Net tft_lcd_b<3> LOC = D7 | IOSTANDARD = LVCMOS33;
Net tft_lcd_b<4> LOC = B9 | IOSTANDARD = LVCMOS33;
Net tft_lcd_b<5> LOC = C9 | IOSTANDARD = LVCMOS33;


#### Module RS232_DTE constraints

Net fpga_0_RS232_DTE_RX_pin LOC =  F16;
Net fpga_0_RS232_DTE_RX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_DTE_TX_pin LOC =  E15;
Net fpga_0_RS232_DTE_TX_pin IOSTANDARD = LVCMOS33;

#### Module LEDs_8Bit constraints

Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> LOC =  R20;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> LOC =  T19;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> LOC =  U20;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> LOC =  U19;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> LOC =  V19;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> LOC =  V20;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> LOC =  Y22;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> LOC =  W21;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> IOSTANDARD = LVCMOS33;

#### Module DIPs_4Bit constraints

Net fpga_0_DIPs_4Bit_GPIO_in_pin<0> LOC =   V8;
Net fpga_0_DIPs_4Bit_GPIO_in_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_DIPs_4Bit_GPIO_in_pin<1> LOC =  U10;
Net fpga_0_DIPs_4Bit_GPIO_in_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_DIPs_4Bit_GPIO_in_pin<2> LOC =   U8;
Net fpga_0_DIPs_4Bit_GPIO_in_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_DIPs_4Bit_GPIO_in_pin<3> LOC =   T9;
Net fpga_0_DIPs_4Bit_GPIO_in_pin<3> IOSTANDARD = LVCMOS33;

#### Module BTNs_4Bit constraints

Net fpga_0_BTNs_4Bit_GPIO_in_pin<0> LOC =  T14;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<0> PULLDOWN;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<1> LOC =  T16;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<1> PULLDOWN;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<2> LOC =  U15;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_BTNs_4Bit_GPIO_in_pin<2> PULLDOWN;

#### Module DDR2_SDRAM constraints

Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin LOC=P1;
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> LOC=R2;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> LOC=T4;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> LOC=R1;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> LOC=U3;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> LOC=U2;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> LOC=U4;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> LOC=U1;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> LOC=Y1;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> LOC=W1;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> LOC=W2;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> LOC=T3;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> LOC=V1;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> LOC=Y2;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> LOC=P3;
Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> LOC=R3;
Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin LOC=M4;
Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin LOC=M3;
Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_CE_pin LOC=N3;
Net fpga_0_DDR2_SDRAM_DDR2_CE_pin IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin LOC=M5;
Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin LOC=N4;
Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin LOC=M1;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin IOSTANDARD = DIFF_SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin LOC=M2;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin IOSTANDARD = DIFF_SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=J3;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=E3;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> IOSTANDARD = SSTL18_I;
Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> LOC=K3;
Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> LOC=K6;
Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> LOC=K2;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> LOC=J5;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> LOC=H1;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> LOC=K5;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> LOC=K1;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> LOC=L3;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> LOC=L5;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> LOC=L1;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> LOC=K4;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> LOC=H2;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> LOC=F2;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> LOC=G4;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> LOC=G1;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> LOC=H6;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> LOC=H5;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> LOC=F1;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> LOC=G3;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> LOC=F3;