user_logic.vhd

Genode FX is a composition of hardware and software components that enable the creation of fully fl

-- Brief  : NPI VGA controller user logic
-- Author : Matthias Alles
-- Date   : 2007-2008
--
-- This component contains the control registers for the NPI_VGA controller.
-- It also takes care about using VGA or DVI output.

--
-- Copyright (C) Genode Labs, Feske & Helmuth Systementwicklung GbR
--               http://www.genode-labs.com
--
-- This file is part of the Genode-FX package, which is distributed
-- under the terms of the GNU General Public License version 2.
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;


entity user_logic is
	generic
	(
	-- ADD USER GENERICS BELOW THIS LINE ---------------
	--USER generics added here
	C_PI_ADDR_WIDTH : integer := 32;  -- fixed for XIL_NPI components
	C_PI_DATA_WIDTH : integer := 64;  -- fixed for XIL_NPI components (since mpmc3 also 32 allowed)
	C_PI_BE_WIDTH   : integer := 8;   -- fixed for XIL_NPI components (since mpmc3 also 4  allowed)
	C_PI_RDWDADDR_WIDTH: integer := 4;-- fixed for XIL_NPI components
	C_NPI_PIXEL_CLK_RATIO : integer := 4;
	C_USE_VGA_OUT : boolean := true;
	C_PIXEL_CLK_GREATER_65MHZ : boolean := false;
	-- ADD USER GENERICS ABOVE THIS LINE ---------------

	-- DO NOT EDIT BELOW THIS LINE ---------------------
	-- Bus protocol parameters, do not add to or delete
	 C_SLV_DWIDTH                   : integer              := 32;
	 C_NUM_REG                      : integer              := 11;
	 C_NUM_INTR                     : integer              := 1
	-- DO NOT EDIT ABOVE THIS LINE ---------------------
 );
 port
 (
	-- ADD USER PORTS BELOW THIS LINE ------------------
	--USER ports added here
	NPI_clk : in std_logic;
	NPI_rst : in std_logic;
	-- VGA/TFT signals
 	clk_pixel     : in  std_logic;
	tft_lcd_hsync : out std_logic;
	tft_lcd_vsync : out std_logic;
	tft_lcd_r : out std_logic_vector(5 downto 2);
	tft_lcd_g : out std_logic_vector(5 downto 2);
	tft_lcd_b : out std_logic_vector(5 downto 2);
	tft_lcd_data  : out std_logic_vector(11 downto 0);
	tft_lcd_de    : out std_logic;
	tft_lcd_clk_n : out std_logic;
	tft_lcd_clk_p : out std_logic;
	tft_lcd_reset : out std_logic;
	tft_lcd_sda   : out std_logic;
	tft_lcd_scl   : out std_logic;
	
	-- MPMC Port Interface - Bus is prefixed with XIL_NPI_ 
	XIL_NPI_Addr : out std_logic_vector(C_PI_ADDR_WIDTH-1 downto 0); 
	XIL_NPI_AddrReq : out std_logic; 
	XIL_NPI_AddrAck : in std_logic; 
	XIL_NPI_RNW : out std_logic; 
	XIL_NPI_Size : out std_logic_vector(3 downto 0); 
	XIL_NPI_InitDone : in std_logic; 
	XIL_NPI_WrFIFO_Data : out std_logic_vector(C_PI_DATA_WIDTH-1 downto 0); 
	XIL_NPI_WrFIFO_BE : out std_logic_vector(C_PI_BE_WIDTH-1 downto 0); 
	XIL_NPI_WrFIFO_Push : out std_logic; 
	XIL_NPI_RdFIFO_Data : in std_logic_vector(C_PI_DATA_WIDTH-1 downto 0); 
	XIL_NPI_RdFIFO_Pop : out std_logic; 
	XIL_NPI_RdFIFO_RdWdAddr: in std_logic_vector(C_PI_RDWDADDR_WIDTH-1 downto 0); 
	XIL_NPI_WrFIFO_AlmostFull: in std_logic; 
	XIL_NPI_WrFIFO_Flush: out std_logic; 
	XIL_NPI_RdFIFO_Empty: in std_logic; 
	XIL_NPI_RdFIFO_Latency: in std_logic_vector(1 downto 0);
	XIL_NPI_RdFIFO_Flush: out std_logic;
	-- ADD USER PORTS ABOVE THIS LINE ------------------

	-- DO NOT EDIT BELOW THIS LINE ---------------------
	-- Bus protocol ports, do not add to or delete
	 Bus2IP_Clk                     : in  std_logic;
	 Bus2IP_Reset                   : in  std_logic;
	 Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
	 Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
	 Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
	 Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
	 IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
	 IP2Bus_RdAck                   : out std_logic;
	 IP2Bus_WrAck                   : out std_logic;
	 IP2Bus_Error                   : out std_logic;
	 IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
	-- DO NOT EDIT ABOVE THIS LINE ---------------------
 );

 attribute SIGIS : string;
 attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
 attribute SIGIS of Bus2IP_Reset  : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

	--USER signal declarations added here, as needed for user logic

	------------------------------------------
	-- Signals for user logic slave model s/w accessible register example
	------------------------------------------
	signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg2                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg3                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg4                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg5                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg6                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg7                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg8                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg9                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg10                      : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg_write_sel              : std_logic_vector(0 to 10);
	signal slv_reg_read_sel               : std_logic_vector(0 to 10);
	signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_read_ack                   : std_logic;
	signal slv_write_ack                  : std_logic;

	------------------------------------------
	-- Signals for user logic interrupt example
	------------------------------------------
	signal intr_flags                   : std_logic_vector(0 to C_NUM_INTR-1);

	signal frame_buffer_address       : std_logic_vector(31 downto 0);
	signal frame_buffer_address_valid : std_logic;
	signal background_color  : std_logic_vector(15 downto 0);

	signal fast_clear_start_address : std_logic_vector(31 downto 0);
	signal fast_clear_init          : std_logic;
	signal fast_clear_pixels        : std_logic_vector(18 downto 0); --  640*480 maximum
	signal fast_clear_done          : std_logic;

	signal low_x_resolution : std_logic;
	signal low_y_resolution : std_logic;
	signal enable_screen    : std_logic;

	component npi_vga is
		generic( 
		C_PI_ADDR_WIDTH : integer := 32;  -- fixed for XIL_NPI components
		C_PI_DATA_WIDTH : integer := 64;  -- fixed for XIL_NPI components
		C_PI_BE_WIDTH   : integer := 8;   -- fixed for XIL_NPI components
		C_PI_RDWDADDR_WIDTH: integer := 4;-- fixed for XIL_NPI components
		C_FB_BASE_ADDR : std_logic_vector := X"00000000";
		C_NPI_PIXEL_CLK_RATIO : integer := 133
		); 
		Port (
		clk   : in std_logic;
		rst   : in std_logic; -- async reset

		frame_buffer_address : in std_logic_vector(31 downto 0);
		frame_buffer_address_valid : in std_logic;
		background_color : in std_logic_vector(15 downto 0);
	
		fast_clear_start_address : in std_logic_vector(31 downto 0);
		fast_clear_init          : in std_logic;
		fast_clear_pixels        : in std_logic_vector(18 downto 0); --  640*480 maximum
		fast_clear_done : out std_logic;

		enable_screen    : in std_logic;
		low_x_resolution : in std_logic;
		low_y_resolution : in std_logic;
		x_res : in unsigned(10 downto 0);
		x_max : in unsigned(10 downto 0);
		hsync_low  : in unsigned(10 downto 0);
		hsync_high : in unsigned(10 downto 0);
		y_res : in  unsigned(9 downto 0);
		y_max : in unsigned(9 downto 0);
		vsync_low  : in unsigned(9 downto 0);
		vsync_high : in unsigned(9 downto 0);
		frame_buffer_size : in unsigned(21 downto 0);
		bgnd_low  : in unsigned(9 downto 0);
		bgnd_high : in unsigned(9 downto 0);

		-- VGA/TFT signals
		tft_lcd_hsync : out std_logic;
		tft_lcd_vsync : out std_logic;
		tft_lcd_r     : out std_logic_vector(4 downto 0);
		tft_lcd_g     : out std_logic_vector(5 downto 0);
		tft_lcd_b     : out std_logic_vector(4 downto 0);
		tft_lcd_de    : out std_logic;
		
		-- MPMC Port Interface - Bus is prefixed with XIL_NPI_ 
		XIL_NPI_Addr : out std_logic_vector(C_PI_ADDR_WIDTH-1 downto 0); 
		XIL_NPI_AddrReq : out std_logic; 
		XIL_NPI_AddrAck : in std_logic; 
		XIL_NPI_RNW : out std_logic; 
		XIL_NPI_Size : out std_logic_vector(3 downto 0); 
		XIL_NPI_InitDone : in std_logic; 
		XIL_NPI_WrFIFO_Data : out std_logic_vector(C_PI_DATA_WIDTH-1 downto 0); 
		XIL_NPI_WrFIFO_BE : out std_logic_vector(C_PI_BE_WIDTH-1 downto 0); 
		XIL_NPI_WrFIFO_Push : out std_logic; 
		XIL_NPI_RdFIFO_Data : in std_logic_vector(C_PI_DATA_WIDTH-1 downto 0); 
		XIL_NPI_RdFIFO_Pop : out std_logic; 
		XIL_NPI_RdFIFO_RdWdAddr: in std_logic_vector(C_PI_RDWDADDR_WIDTH-1 downto 0); 
		XIL_NPI_WrFIFO_AlmostFull: in std_logic; 
		XIL_NPI_WrFIFO_Flush: out std_logic; 
		XIL_NPI_RdFIFO_Empty: in std_logic; 
		XIL_NPI_RdFIFO_Latency: in std_logic_vector(1 downto 0);
		XIL_NPI_RdFIFO_Flush: out std_logic 
	);
	end component;

	component iic_init port(
		clk     : in  std_logic;
		reset_n : in  std_logic;
		Pixel_clk_greater_than_65MHz: in  std_logic;
		SDA     : out std_logic;
		SCL     : out std_logic;
		done    : out std_logic);
	end component;

	component tft_if port(
		clk:                    in std_logic;
		rst:                    in std_logic;
		HSYNC:                  in std_logic;
		VSYNC:                  in std_logic;
		DE:                     in std_logic;
		R0:                     in std_logic;
		R1:                     in std_logic;
		R2:                     in std_logic;
		R3:                     in std_logic;
		R4:                     in std_logic;
		R5:                     in std_logic;
		G0:                     in std_logic;
		G1:                     in std_logic;                                   
		G2:                     in std_logic;
		G3:                     in std_logic;
		G4:                     in std_logic;
		G5:                     in std_logic;
		B0:                     in std_logic;
		B1:                     in std_logic;
		B2:                     in std_logic;
		B3:                     in std_logic;
		B4:                     in std_logic;   
		B5:                     in std_logic;
		TFT_LCD_HSYNC:          out std_logic;
		TFT_LCD_VSYNC:          out std_logic;
		TFT_LCD_DE:             out std_logic;
		TFT_LCD_CLK_P:          out std_logic;
		TFT_LCD_CLK_N:          out std_logic;
		TFT_LCD_DATA0:          out std_logic;
		TFT_LCD_DATA1:          out std_logic;
		TFT_LCD_DATA2:          out std_logic;
		TFT_LCD_DATA3:          out std_logic;
		TFT_LCD_DATA4:          out std_logic;
		TFT_LCD_DATA5:          out std_logic;
		TFT_LCD_DATA6:          out std_logic;
		TFT_LCD_DATA7:          out std_logic;
		TFT_LCD_DATA8:          out std_logic;
		TFT_LCD_DATA9:          out std_logic;
		TFT_LCD_DATA10:         out std_logic;
		TFT_LCD_DATA11:         out std_logic);
	end component;

	signal dvi_init_done : std_logic;
	signal pixel_clk_greater_than_65mhz : std_logic;

	signal tft_lcd_data0 : std_logic;
	signal tft_lcd_data1 : std_logic;
	signal tft_lcd_data2 : std_logic;
	signal tft_lcd_data3 : std_logic;
	signal tft_lcd_data4 : std_logic;
	signal tft_lcd_data5 : std_logic;
	signal tft_lcd_data6 : std_logic;
	signal tft_lcd_data7 : std_logic;
	signal tft_lcd_data8 : std_logic;
	signal tft_lcd_data9 : std_logic;
	signal tft_lcd_data10 : std_logic;
	signal tft_lcd_data11 : std_logic;

	signal vsync_rst : std_logic;
	signal fast_clear_done_t : std_logic;

	signal tft_lcd_hsync_int   : std_logic;
	signal tft_lcd_vsync_int   : std_logic;
	signal tft_lcd_vsync_int_t : std_logic;

	signal tft_lcd_r_int : std_logic_vector(4 downto 0);
	signal tft_lcd_g_int : std_logic_vector(5 downto 0);
	signal tft_lcd_b_int : std_logic_vector(4 downto 0);

	signal tft_lcd_r_t1 : std_logic_vector(4 downto 0);
	signal tft_lcd_g_t1 : std_logic_vector(5 downto 0);
	signal tft_lcd_b_t1 : std_logic_vector(4 downto 0);
	signal tft_lcd_r_t2 : std_logic_vector(4 downto 0);
	signal tft_lcd_g_t2 : std_logic_vector(5 downto 0);
	signal tft_lcd_b_t2 : std_logic_vector(4 downto 0);
	signal tft_lcd_hsync_t1   : std_logic;
	signal tft_lcd_vsync_t1   : std_logic;
	signal tft_lcd_hsync_t2   : std_logic;
	signal tft_lcd_vsync_t2   : std_logic;

	signal de_npi_clk   : std_logic;
	signal de_pixel_clk : std_logic;
	signal de_sync_pipe : std_logic_vector(2 downto 0);
	signal de_level_flag: std_logic;
	signal rst_n : std_logic;

	signal x_res : unsigned(10 downto 0);
	signal x_max : unsigned(10 downto 0);
	signal hsync_low  : unsigned(10 downto 0);
	signal hsync_high : unsigned(10 downto 0);
	signal y_res : unsigned(9 downto 0);
	signal y_max : unsigned(9 downto 0);
	signal vsync_low  : unsigned(9 downto 0);
	signal vsync_high : unsigned(9 downto 0);
	signal frame_buffer_size : unsigned(21 downto 0);
	signal bgnd_low  : unsigned(9 downto 0);
	signal bgnd_high : unsigned(9 downto 0);

begin

	pixel_clk_greater_than_65mhz <= '1' when C_PIXEL_CLK_GREATER_65MHZ = true else '0';

	dvi_out: if C_USE_VGA_OUT = false generate
		dvi_iic_init: iic_init port map(
			clk     => Bus2IP_Clk,
			reset_n => rst_n,
			Pixel_clk_greater_than_65MHz => pixel_clk_greater_than_65mhz,
			SDA     =>  TFT_LCD_SDA,
			SCL     =>  TFT_LCD_SCL,
			done    =>  dvi_init_done);
	
		rst_n <= not BUS2IP_Reset;
		tft_lcd_reset <= rst_n;

		-- synchronize the high frequency signals to the pixel clock
		process(NPI_clk, Bus2IP_Reset) is
		begin
			if Bus2IP_Reset = '1' then
				de_level_flag <= '0';
			elsif NPI_clk'event and NPI_clk = '1' then
				if de_npi_clk = '1' then
					de_level_flag <= not de_level_flag;
				end if;
			end if;
		end process;

		process(clk_pixel, Bus2IP_Reset) is
		begin
			if Bus2IP_Reset = '1' then
				de_sync_pipe <= (others => '0');
				tft_lcd_r_t1 <= (others => '0');
				tft_lcd_g_t1 <= (others => '0');
				tft_lcd_b_t1 <= (others => '0');
				tft_lcd_r_t2 <= (others => '0');
				tft_lcd_g_t2 <= (others => '0');
				tft_lcd_b_t2 <= (others => '0');
				tft_lcd_hsync_t1 <= '0';
				tft_lcd_hsync_t2 <= '0';
				tft_lcd_vsync_t1 <= '0';
				tft_lcd_vsync_t2 <= '0';
			elsif clk_pixel'event and clk_pixel = '1' then