subdds.mdl

generate the sine wave using DSP Builder

	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_AltBus.fixedpointlog"
	}
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	  Ports			  [1, 1]
	  Position		  [90, 312, 155, 328]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Signed Integer"
	  bwl			  "10"
	  bwr			  "0"
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	  floatingPointOutput	  on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Amp.fixedpointlog"
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	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Bus Conversion"
	  SourceType		  "Bus Conversion AlteraBlockset"
	  BusType		  "Signed Integer"
	  ibwl			  "20"
	  ibwr			  "1"
	  bwl			  "16"
	  bwr			  "1"
	  bitToConnectToOutputLSB "3"
	  round			  off
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	Block {
	  BlockType		  Reference
	  Name			  "Bus Conversion1"
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	  Position		  [85, 240, 145, 260]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Bus Conversion"
	  SourceType		  "Bus Conversion AlteraBlockset"
	  BusType		  "Signed Integer"
	  ibwl			  "32"
	  ibwr			  "1"
	  bwl			  "10"
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	  bitToConnectToOutputLSB "22"
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	Block {
	  BlockType		  Reference
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	  Position		  [190, 107, 250, 163]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Delay"
	  SourceType		  "Delay AlteraBlockset"
	  pipeline		  "1"
	  pipeline_display	  "1"
	  ClockPhase		  "1"
	  use_ena		  off
	  use_sclr		  off
	  allowFloatingPointOverride on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Delay.fixedpointlog"
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	  ForegroundColor	  "blue"
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	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Signed Integer"
	  bwl			  "32"
	  bwr			  "0"
	  saturate		  off
	  floatingPointInput	  on
	  floatingPointOutput	  on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Freqword.fixedpointlog"
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	Block {
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	  Name			  "Freqword1"
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	  Position		  [90, 27, 155, 43]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/AltBus"
	  SourceType		  "AltBus AlteraBlockset"
	  BusType		  "Signed Integer"
	  bwl			  "32"
	  bwr			  "0"
	  saturate		  off
	  floatingPointInput	  on
	  floatingPointOutput	  on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Freqword1.fixedpointlog"
	}
	Block {
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	  Position		  [580, 257, 645, 273]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Output"
	  SourceType		  "Output AlteraBlockset"
	  iofile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Output.capture"
	  BusType		  "Signed Integer"
	  bwl			  "16"
	  bwr			  "0"
	  externalType		  "Inferred"
	  PORTTYPE		  "Output"
	  allowFloatingPointOverride on
	  logOutputs		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Parallel Adder Subtractor"
	  Ports			  [2, 1]
	  Position		  [350, 77, 385, 153]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Parallel Adder Subtractor"
	  SourceType		  "ParallelAdder AlteraBlockset"
	  number_of_inputs	  "2"
	  direction		  "++"
	  use_pipeline		  on
	  pipeline_display	  "1"
	  phase_selection	  "1"
	  use_ena		  off
	  use_aclr		  off
	  allowFloatingPointOverride on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Parallel+Adder+Subtractor.fixedpointlog"
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	Block {
	  BlockType		  Reference
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	  Position		  [550, 57, 585, 133]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/Parallel Adder Subtractor"
	  SourceType		  "ParallelAdder AlteraBlockset"
	  number_of_inputs	  "2"
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	  use_pipeline		  on
	  pipeline_display	  "1"
	  phase_selection	  "1"
	  use_ena		  off
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	  allowFloatingPointOverride on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Parallel+Adder+Subtractor1.fixedpointlog"
	}
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	  BusType		  "Signed Integer"
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	  pipeline_display	  "2"
	  phase_selection	  "1"
	  use_ena		  off
	  use_aclr		  off
	  UseLPM		  off
	  UseDedicatedCircuitry	  on
	  allowFloatingPointOverride on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_Product.fixedpointlog"
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	Block {
	  BlockType		  Reference
	  Name			  "SinLUT"
	  Ports			  [1, 1]
	  Position		  [210, 199, 275, 301]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder2/LUT"
	  SourceType		  "LUT AlteraBlockset"
	  addr_width		  "10"
	  BusType		  "Signed Integer"
	  bwl			  "10"
	  bwr			  "0"
	  init_array		  "255*sin( [0:2*pi/(2^10):2*pi] )"
	  allowFloatingPointOverride on
	  logOutputs		  off
	  logFile		  "C:\\Documents and Settings\\Administrator\\My Documents\\MATLAB\\tb_SubDDS\\SubDDS_SinGen_SinLUT.fixedpointlog"
	  use_ena		  off
	  reg_data		  off
	  use_lpm		  on
	  reg_addr		  off
	  ram_type		  "AUTO"
	  pipeline_display	  "1"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [665, 173, 695, 187]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out2"
	  Position		  [665, 203, 695, 217]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "SinOut"
	  Position		  [665, 258, 695, 272]
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "Freqword"
	  SrcPort		  1
	  DstBlock		  "Delay"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  DstBlock		  "Parallel Adder Subtractor"
	  DstPort		  2
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	Line {
	  SrcBlock		  "AltBus"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Parallel Adder Subtractor1"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -60; -185, 0; 0, 40]
	    DstBlock		    "Parallel Adder Subtractor"
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	  }
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	Line {
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	  SrcPort		  1
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	  DstPort		  1
	}
	Line {
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	  SrcPort		  1
	  Points		  [55, 0; 0, 85]
	  Branch {
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	    DstBlock		    "Bus Conversion1"
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	  }
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	  Points		  [360, 0; 0, 40]
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	}
	Line {
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	  DstBlock		  "SinLUT"
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	}
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	  SrcBlock		  "SinLUT"
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	  Branch {
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	  Points		  [150, 0; 0, -40]
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	Line {
	  SrcBlock		  "Output"
	  SrcPort		  1
	  DstBlock		  "SinOut"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Bus Conversion"
	  SrcPort		  1
	  DstBlock		  "Output"
	  DstPort		  1
	}
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	  SrcBlock		  "Product"
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	}
	Line {
	  SrcBlock		  "Pin[31:0]"
	  SrcPort		  1
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	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Fin[31:0]"
	  SrcPort		  1
	  DstBlock		  "Freqword"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AIn[9;0]"
	  SrcPort		  1
	  DstBlock		  "Amp"
	  DstPort		  1
	}
      }
    }
    Line {
      SrcBlock		      "SinGen"
      SrcPort		      3
      DstBlock		      "Scope"
      DstPort		      3
    }
    Line {
      SrcBlock		      "SinGen"
      SrcPort		      1
      Points		      [30, 0]
      DstBlock		      "Scope"
      DstPort		      1
    }
    Line {
      SrcBlock		      "SinGen"
      SrcPort		      2
      Points		      [0, 20]
      DstBlock		      "Scope"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Constant"
      SrcPort		      1
      DstBlock		      "AltBus1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Constant1"
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      DstBlock		      "AltBus"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Constant2"
      SrcPort		      1
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      DstPort		      1
    }
    Line {
      SrcBlock		      "AltBus2"
      SrcPort		      1
      DstBlock		      "SinGen"
      DstPort		      3
    }
    Line {
      SrcBlock		      "AltBus"
      SrcPort		      1
      DstBlock		      "SinGen"
      DstPort		      2
    }
    Line {
      SrcBlock		      "AltBus1"
      SrcPort		      1
      DstBlock		      "SinGen"
      DstPort		      1
    }
  }
}