denise.v

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// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is Denise
// This module	is a complete implementation of the Amiga OCS Denise chip
// It supports all OCS modes including HAM, EHB and interlaced video
//
// 11-05-2005		-started coding
// 15-05-2005		-added local beamcounter
//				-added bitplanes module
//				-added color registers
//				-first experimental version
// 22-05-2005		-added diwstrt/diwstop
// 12-06-2005		-started integrating sprites module
// 21-06-2005		-done more work on integrating sprites module
// 22-06-2005		-done more work on completing denise
// 27-06-2005		-added main priority logic (sprites vs playfields)
// 28-06-2005		-added hold and modify mode
//				-added delay register and video multiplexers
//				-added video output register
// 29-06-2005		-added collision detection, Denise is now complete! (but untested)
//				-(later this day) Denise works! (hires,interlaced,playfield,sprites)
// 07-08-2005		-added deniseid register
// 02-10-2005		-fixed bit 15 of CLXDAT high
// 19-10-2005		-code now uses sol signal to synchronize local beam counter
// 11-01-2006		-added blanking circuit
// 22-01-2006		-added vertical window clipping
//JB:
// 2008-07-08		-added hires output (for scandoubler)
//					-changed Denise ID (sometimes Show Config detected wrong chip type)


module Denise
(
	input 	clk,		   			//bus clock / lores pixel clock
	input 	reset,					//reset
	input	sol,					//start of video line
	input	sof,					//start of video frame 
	input	strhor,					//horizontal strobe
	input 	[8:1]regaddress,		//register adress inputs
	input 	[15:0]datain,			//bus data in
	output 	[15:0]dataout,		//bus data out
	input	blank,					//blanking input
	output 	[3:0]red, 			//red componenent video out
	output 	[3:0]green,  			//green component video out
	output 	[3:0]blue,			//blue component video out
	output	reg hires				//hires
);

//register names and adresses		
parameter DIWSTRT=9'h08e;
parameter DIWSTOP=9'h090;
parameter BPLCON0=9'h100;  		
parameter BPLCON2=9'h104; 
parameter DENISEID=9'h07c;

//local signals
reg		[8:0]horbeam;			//horizontal beamcounter
reg		[8:0]verbeam;			//vertical beamcounter
reg		homod;					//HAM mode select
reg		dblpf;					//double playfield select
reg		[6:0]bplcon2;			//bplcon2 (playfield video priority) register

wire	dclk;					//ddr register select clock

reg		[15:0]diwstrt;		//vertical/horizontal display window start position
reg		[15:0]diwstop;		//vertical/horizontal display window stop position

wire	[6:1]bpldata;			//raw bitplane serial video data
wire	[3:0]sprdata;			//sprite serial video data
wire	[5:0]plfdata;			//playfield serial video data
wire	[2:1]nplayfield;		//playfield 1,2 valid data signals
wire	[7:0]nsprite;			//sprite 0-7 valid data signals 
wire	sprsel;					//sprite select

wire	[11:0]hamrgb;			//hold and modify mode RGB video data
wire	[5:0]plfdata_d;		//plfdata delayed by one low res pixel
wire	sprsel_d;				//sprsel delayed by one low res pixel
reg		[3:0]sprdata_d;		//sprdata delayed by one low res pixel

reg		[5:0]tabledata;		//color table color select in
wire	[11:0]tablergb;		//color table rgb data out
reg		[11:0]outrgb;			//final multiplexer rgb output data
wire	window;					//window enable signal

wire	[15:0]idout; 			//deniseid dataout
wire	[15:0]colout;			//colision detection dataout

//--------------------------------------------------------------------------------------

//data out mulitplexer
assign dataout=colout|idout;

//--------------------------------------------------------------------------------------

//generate dclk dclk is in sync with clk but driven by logic instead of general clock
//dclk is used to drive the multiplexers of the double data rate (hires) registers
reg dclkl1;
reg dclkl2;
always @(posedge clk)
	dclkl1<=~dclkl1;
always @(negedge clk)
	dclkl2<=dclkl1;
assign dclk=dclkl1^dclkl2;

//--------------------------------------------------------------------------------------

//Denise local horizontal beamcounter
always @(posedge clk)
	if (strhor)
		horbeam <= 16;
	else
		horbeam <= horbeam + 1;

//Denise local vertical beamcounter
always @(posedge clk)
	if (sof)
		verbeam <= 0;
	else if (sol)
		verbeam <= verbeam + 1;

//--------------------------------------------------------------------------------------

//bplcon0 register
always @(posedge clk)
	if(reset)
	begin
		hires<=0;
		homod<=0;
		dblpf<=0;
	end
	else if(regaddress[8:1]==BPLCON0[8:1])
	begin
		hires<=datain[15];
		homod<=datain[11];
		dblpf<=datain[10];
	end	

//bplcon2 register
always @(posedge clk)
	if(reset)
		bplcon2<=0;
	else if(regaddress[8:1]==BPLCON2[8:1])
		bplcon2[6:0]<=datain[6:0];

//diwstart and diwstop registers (vertical and horizontal limits of display window)
always @(posedge clk)
	if(regaddress[8:1]==DIWSTRT[8:1])
		diwstrt[15:0]<=datain[15:0];
always @(posedge clk)
	if(regaddress[8:1]==DIWSTOP[8:1])
		diwstop[15:0]<=datain[15:0];

assign idout = regaddress[8:1]==DENISEID[8:1] ? 16'hFF_FF : 16'b00000000_00000000;

//--------------------------------------------------------------------------------------

//generate window enable signal
//(true when beamcounter satisfies vertical/horizontal diwstrt/diwstop limits)

//horizontal window limits
reg	hwindow;
always @(posedge clk)
	if(horbeam[8:0]=={1'b0,diwstrt[7:0]})
		hwindow<=1;
	else if(horbeam[8:0]=={1'b1,diwstop[7:0]})
		hwindow<=0;
//vertical window limits
reg	vwindow;
always @(posedge clk)
	if(verbeam[8:0]=={1'b0,diwstrt[15:8]})
		vwindow<=1;
	else if(verbeam[8:0]=={~diwstop[15],diwstop[15:8]})
		vwindow<=0;
//combined window enable signal
assign window=hwindow&vwindow;

//--------------------------------------------------------------------------------------

//instantiate bitplane module
bitplanes bplm0 (	.clk(clk),
				.regaddress(regaddress),
				.datain(datain),
				.hires(hires),
				.bpldata(bpldata)	);

//instantiate playfield module
playfields plfm0 (	.bpldata(bpldata),
				.dblpf(dblpf),
				.pf2pri(bplcon2[6]),
				.nplayfield(nplayfield),
				.plfdata(plfdata)	);

//instantiate sprite module
sprites sprm0 (	.clk(clk),
				.reset(reset),
				.regaddress(regaddress),
				.horbeam(horbeam),
				.datain(datain),
				.nsprite(nsprite),
				.sprdata(sprdata)	);

//instantiate video priority logic module
sprpriority spm0 (	.bplcon2(bplcon2[5:0]),
				.nplayfield(nplayfield),
				.nsprite(nsprite),
				.sprsel(sprsel)	);

//instantiate color table
colortable ctbm0 (	.clk(clk),
				.regaddress(regaddress),
				.datain(datain[11:0]),
				.select(tabledata),
				.rgb(tablergb)		);

//instantiate HAM (hold and modify) module
hamgenerator ham0 (	.clk(clk),
				.regaddress(regaddress),
				.datain(datain[11:0]),
				.bpldata(bpldata),
				.rgb(hamrgb)		);

//instantiate collision detection module
collision col0 (	.clk(clk),
				.reset(reset),
				.regaddress(regaddress),
				.datain(datain),
				.dataout(colout),
				.bpldata(bpldata),
				.nsprite(nsprite)	);

//--------------------------------------------------------------------------------------

//sprsel and plfdata latch (ddr)
//delay those signals by one low res pixel 
reg [6:0]plfdatal1;
reg [6:0]plfdatal2;
always @(negedge clk)
	plfdatal1<={sprsel,plfdata[5:0]};
always @(posedge clk)
	plfdatal2<={sprsel,plfdata[5:0]};
assign {sprsel_d,plfdata_d[5:0]}=(dclk)?plfdatal1:plfdatal2;

//--------------------------------------------------------------------------------------

//sprdata latch (sdr)
//delay sprdata by one low res pixel 
always @(posedge clk)
	sprdata_d<=sprdata;

//--------------------------------------------------------------------------------------

//sprdata_d / plfdata_d / border multiplexer
always @(homod or sprsel_d or window or sprdata_d or plfdata_d)