agnus.v

Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer.

// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is Agnus 
// The copper, blitter and sprite dma have a reqdma output and an ackdma input
// if they are ready for dma they do a dma request by asserting reqdma
// the dma priority logic circuit then checks which module is granted access by 
// looking at their priorities and asserting the ackdma signal of the module that
// has the highest priority
//
// Other dma channels (bitplane, audio and disk) only have an enable input (bitplane)
// or only a dma request input from Paula (dmal input, disk and audio) 
// and an dma output to indicate that they are using their slot.
// this is because they have the highest priority in the system and cannot be hold up
//
// The bus clock runs at 7.09MHz which is twice as fast as in the original amiga and
// the same as the pixel clock / horizontal beam counter.
//
// general cycle allocation is as follows:
// (lowest 2 bits of horizontal beam counter)
//
// slot 0:	68000 (priority in that order, extra slots because of higher bus speed)
// slot 1:	disk, bitplanes, copper, blitter and 68000 (priority in that order)   	
// slot 2:	blitter and 68000 (priority in that order, extra slots because of higher bus speed)
// slot 3:	disk, bitplanes, sprites, audio and 68000 (priority in that order)
//
// because only the odd slots are used by the chipset, the chipset runs at the same 
// virtual speed as the original. The cpu gets the extra even slots allowing for
// faster cpu's without the need for an extra fastram controller
// Blitter timing is not completely accurate, it uses slot 1 and 2 instead of 1 and 3, this is to let
// the blitter not slow down too much dma contention. (most compatible solution for now)
// Blitter nasty mode activates the buspri signal to indicate to gary to stop access to the chipram/chipregisters.
// Blitter nasty mode is only activated if blitter activates bltpri cause it depends on blitter settings if blitter
// will really block the cpu.
//
// 19-03-2005		-first serious version
//				-added clock generator
// 20-03-2005		-fixed regaddress idle state
// 				-more reliable 3-state timing
// 27-03-2005		-fixed bug in regadress generator, adress was not set to idle if
//				 chip bus was idle (hwr,lwr and rd low)
// 10-04-2005		-added real clock generator
// 11-04-2005		-removed rd,hwr and lwr signals due to change in address decoder
// 24-04-2005		-adapted to new 7.09 MHz bus clock
// 				-added more complete dmaslot controller
// 25-04-2005		-continued work on beam counters
// 26-04-2005		-continued work on beam counters
// 02-05-2005		-moved beam counter to seperate module
//				-done work on bitplane dma engine
// 05-05-2005		-completed first version of bitplane dma engine (will it work ?)
//				-adapted code for bitplane dma engine
// 15-05-2005		-added horbeam reset output and start of vertical blank interrupt output
//				-fixed small bug in bpldma_engine
//				-changed horizontal sync/blank timing so image is centered on screen
//				-made some changes to interlaced vertical sync timing
//17-05-2005		-fixed bug in bpldma_engine, modulo was not added right
//18-05-2005		-fixed hires bitplane data fetch
//				-interlaced is now selected through bplcon0
//22-05-2005		-changed name of diwstrt/stop to vdiwstrt/stop to make code clearer
//29-05-2005		-added copper but its needs some more work to be integrated properly
//31-05-2005		-added support for negative modulo in bitplane dma engine
//				-integrated copper better
//06-06-2005		-started coding of sprite dma engine
//				-cleaned up code a bit (comments, spaces between lines and so on)
//07-06-2005		-done work on sprite dma engine
//08-06-2005		-done more work on sprite dma engine
//12-06-2005		-first finished version of sprite dma engine
//				-integrated sprite dma engine into agnus
//28-06-2005		-delayed horizontal sync/blanking by 2 low res pixels to compensate
//				 for pipelining delay in Denise
//19-07-2005		-changed phase of cpu clock in an attempt to solve kickstart boot problem
//20-07-2005		-changed phase of cpu clock back again, it was not the problem..
//31-07-2005		-fixed bbusy to 1 as it is not yet implemented
//07-08-2005		-added ersy bit, if enabled the beamcounters stop counting
//				-bit 11 and 12 of dmacon are now also implemented
//04-09-2005		-added blitter finished interrupt
//				-added blitter
//05-09-2005		-did some dma cycle allocation testing
//11-09-2005		-testing
//18-09-2005		-removed ersy support, this seems to cure part of the kickstart 1.2 problems
//20-09-2005		-testing
//21-09-2005		-added copper disable input for testing
//23-09-2005		-moved VPOSR/VHPOSR handling to beamcounter module
//				-added VPOS/VHPOSW registers
//19-10-2005		-removed burst clock and cck (color clock enable) outputs
//				-removed hcres,vertb and intb outputs
//				-added sol,sof and int3 outputs
//				-adapted code to use new signals
//23-10-2005		-added dmal signal
//				-added disk dma engine
//21-10-2005		-fixed bug in disk dma engine, DSKDATR and DSKDAT addresses were swapped
//04-12-2005		-added magic mystery logic to handle ddfstrt/ddfstop
//14-12-2005		-fixed some sensitivity lists
//21-12-2005		-added rd,hwr and lwr inputs
//				-added bus,buswr and buspri outputs
//26-12-2005		-fixed buspri output
//				-changed blitter nasty mode altogether, it is now not according to the HRM,
//				 but at least this solution seems to work for most games/demos
//27-12-2005		-added audio dma engine
//28-12-2005		-fixed audio dma engine
//29-12-2005		-rewritten audio dma engine
//03-01-2006		-added dmas to avoid interference with copper cycles
//07-01-2006		-also added dmas to disk dma engine
//11-01-2006		-removed ability to write beam counters
//22-01-2006		-removed composite sync output
//				-added ddfstrt/ddfstop HW limits
//23-01-2006		-added fastblitter enable input
//25-01-2006		-improved blitter nasty timing
//14-02-2006		-again improved blitter timing, this seems the most compatible solution for now..
//19-02-2006		-again improved blitter timing, this is an even more compatible solution

//JB:
//2008-07-17		- modified display dma engine to be more compatible
//					- moved beamcounters to separate module
//					- heavily modified sprite dma engine

module Agnus
(
	input 	clk,					//clock
	input	clk28m,					//28MHz clock
	input	reset,					//reset
	input 	aen,					//bus adress enable (register bank)
	input	rd,						//bus read
	input	hwr,					//bus high write
	input	lwr,					//bus low write
	input	[15:0]datain,			//data bus in
	output	[15:0]dataout,		//data bus out
	input 	[8:1]addressin,		//256 words (512 bytes) adress input,
	output	reg [20:1]addressout,	//chip address output,
	output 	reg [8:1]regaddress,	//256 words (512 bytes) register address out,
	output	reg bus,				//agnus needs bus
	output	reg buswr,				//agnus does a write cycle
	output	buspri,					//agnus blitter has priority in chipram
	output	_hsync,					//horizontal sync
	output	_vsync,					//vertical sync
	output	blank,					//video blanking
	output	sol,					//start of video line (active during last pixel of previous line) 
	output	sof,					//start of video frame (active during last pixel of previous frame)
	output	strhor,					//horizontal strobe for Denise (helps to solve some extreme overscan isues)
	output	int3,					//blitter finished interrupt (to Paula)
	input	dmal,					//dma request (from Paula)
	input	dmas,					//dma special (from Paula)
	input	ntsc,					//chip is NTSC
	input	fastchip				//DEBUG fast chipram access enable
);

//register names and adresses		
parameter DMACON  = 9'h096;
parameter DMACONR = 9'h002;
parameter DIWSTRT = 9'h08e;
parameter DIWSTOP = 9'h090;

//local signals
reg		[15:0]dmaconr;		//dma control read register

wire	[8:0]horbeam;			//horizontal beam counter
wire	[10:0]verbeam;		//vertical beam counter
wire	interlace;				//interlace enable

wire	vbl;					///JB: vertical blanking
wire	vblend;					///JB: last line of vertical blanking

wire	bbusy;					//blitter busy status
wire	bzero;					//blitter zero status
wire	bblck;					//blitter blocks cpu
wire	bltpri;					//blitter nasty
wire	bplen;					//bitplane dma enable
wire	copen;					//copper dma enable
wire	blten;					//blitter dma enable
wire	spren;					//sprite dma enable

reg		[15:8]vdiwstrt;		//vertical window start position
reg		[15:8]vdiwstop;		//vertical window stop position

wire	dma_bpl;				//bitplane dma engine uses it's slot
wire	dma_dsk;				//disk dma uses it's slot
wire	dma_aud;				//audio dma uses it's slot
reg		ack_cop;				//copper dma acknowledge
wire	req_cop; 				//copper dma request
reg		ack_blt;				//blitter dma acknowledge
wire	req_blt; 				//blitter dma request
reg		ack_spr;				//sprite dma acknowledge
wire	req_spr; 				//sprite dma request
wire	[15:0]data_bmc;		//beam counter data out
wire	[20:1]address_dsk;	//disk dma engine chip address out
wire	[8:1]regaddress_dsk; 	//disk dma engine register address out
wire	wr_dsk;					//disk dma engine write enable out
wire	[20:1]address_aud;	//audio dma engine chip address out
wire	[8:1]regaddress_aud; 	//audio dma engine register address out
wire	[20:1]address_bpl;	//bitplane dma engine chip address out
wire	[8:1]regaddress_bpl; 	//bitplane dma engine register address out
wire	[20:1]address_spr;	//sprite dma engine chip address out
wire	[8:1]regaddress_spr; 	//sprite dma engine register address out
wire	[20:1]address_cop;	//copper dma engine chip address out
wire	[8:1]regaddress_cop; 	//copper dma engine register address out
wire	[20:1]address_blt;	//blitter dma engine chip address out
wire	[15:0]data_blt;		//blitter dma engine data out
wire	wr_blt;					//blitter dma engine write enable out
wire	[8:1]regaddress_cpu;	//cpu register address

//--------------------------------------------------------------------------------------

//data out multiplexer
assign dataout=data_bmc|dmaconr|data_blt;

//cpu address decoder
assign regaddress_cpu=(aen&(rd|hwr|lwr))?addressin:8'hff;

//blitter nasty mode output (blocks cpu)
//(when blitter dma is active AND blitter nasty mode is on AND blitter indicates to block cpu)
//(also when fastchip is false, all even cycles are also blocked giving A500 chipram speed)
assign buspri=(blten&bltpri&bblck) | (~horbeam[0]&~fastchip);

//--------------------------------------------------------------------------------------

//chip address, register address and control signal multiplexer
//AND dma priority handler
//first item in this if else if list has highest priority
always @(	dma_dsk or address_dsk or regaddress_dsk or wr_dsk or
		dma_aud or address_aud or regaddress_aud or
		dma_bpl or address_bpl or regaddress_bpl or req_cop or 
		copen or address_cop or regaddress_cop or regaddress_cpu
		or spren or req_spr or address_spr or regaddress_spr
		or blten or req_blt or address_blt or wr_blt)
begin
	if(dma_dsk)//busses allocated to disk dma engine
	begin
		bus=1;
		ack_cop=0;
		ack_blt=0;
		ack_spr=0;
		addressout=address_dsk;
		regaddress=regaddress_dsk;
		buswr=wr_dsk;
	end
	else if(dma_aud)//busses allocated to audio dma engine
	begin
		bus=1;
		ack_cop=0;
		ack_blt=0;
		ack_spr=0;
		addressout=address_aud;
		regaddress=regaddress_aud;
		buswr=0;
	end
	else if(dma_bpl)//busses allocated to bitplane dma engine
	begin
		bus=1;
		ack_cop=0;
		ack_blt=0;
		ack_spr=0;
		addressout=address_bpl;
		regaddress=regaddress_bpl;
		buswr=0;
	end
	else if(req_spr && spren)//busses allocated to sprite dma engine
	begin
		bus=1;
		ack_cop=0;
		ack_blt=0;
		ack_spr=1;
		addressout=address_spr;
		regaddress=regaddress_spr;
		buswr=0;
	end
	else if(req_cop && copen)//busses allocated to copper
	begin
		bus=1;
		ack_cop=1;
		ack_blt=0;
		ack_spr=0;
		addressout=address_cop;
		regaddress=regaddress_cop;
		buswr=0;
	end
	else if(req_blt && blten)//busses allocated to blitter
	begin
		bus=1;
		ack_cop=0;
		ack_blt=1;
		ack_spr=0;
		addressout=address_blt;
		regaddress=8'hff;
		buswr=wr_blt;
	end
	else//busses not allocated by agnus
	begin
		bus=0;
		ack_cop=0;
		ack_blt=0;
		ack_spr=0;
		addressout=0;
		regaddress=regaddress_cpu;//pass register addresses from cpu address bus
		buswr=0;
	end
end

//--------------------------------------------------------------------------------------

reg	[12:0]dmacon;

//dma control register read
always @(regaddress or bbusy or bzero or dmacon)
	if(regaddress[8:1]==DMACONR[8:1])
		dmaconr[15:0]<={1'b0,bbusy,bzero,dmacon[12:0]};
	else
		dmaconr<=0;

//dma control register write
always @(posedge clk)
	if(reset)
		dmacon<=0;
	else if(regaddress[8:1]==DMACON[8:1])
	begin
		if(datain[15])
			dmacon[12:0]<=dmacon[12:0]|datain[12:0];
		else
			dmacon[12:0]<=dmacon[12:0]&(~datain[12:0]);	
	end

//assign dma enable bits
assign	bltpri=dmacon[10];
assign	bplen=dmacon[8]&dmacon[9];
assign	copen=dmacon[7]&dmacon[9];
assign	blten=dmacon[6]&dmacon[9];
assign	spren=dmacon[5]&dmacon[9];
										
//--------------------------------------------------------------------------------------

//write diwstart and diwstop registers
always @(posedge clk)
	if(regaddress[8:1]==DIWSTRT[8:1])
		vdiwstrt[15:8]<=datain[15:8];
always @(posedge clk)
	if(regaddress[8:1]==DIWSTOP[8:1])
		vdiwstop[15:8]<=datain[15:8];

//--------------------------------------------------------------------------------------

//instantiate disk dma engine
dskdma_engine dsk1
(
	.clk(clk),
	.dma(dma_dsk),
	.dmal(dmal),
	.dmas(dmas),
	.horbeam(horbeam),
	.wr(wr_dsk),
	.regaddressin(regaddress),
	.regaddressout(regaddress_dsk),
	.datain(datain),
	.addressout(address_dsk)	
);

//--------------------------------------------------------------------------------------

//instantiate audio dma engine
auddma_engine aud1
(
	.clk(clk),
	.dma(dma_aud),
	.dmal(dmal),
	.dmas(dmas),
	.horbeam(horbeam),
	.regaddressin(regaddress),
	.regaddressout(regaddress_aud),
	.datain(datain),
	.addressout(address_aud)
);

//--------------------------------------------------------------------------------------

//instantiate bitplane dma
reg	bplenable;
always @(bplen or verbeam or vdiwstrt or vdiwstop)//bitplane dma enabled if vertical beamcounter within limits set by diwstrt and diwstop