minimig1.v

Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer.

	.clk(clk),
	.aen(selciaa),
	.rd(rd),
	.wr(lwr),
	.reset(reset),
	.rs(address[11:8]),
	.datain(data[7:0]),
	.dataout(ciadataout[7:0]),
	.tick(sof),//vsync count
	.e(e),
	.irq(int2),
	.portain({_fire1,_fire0,_ready,_track0,_wprot,_change}),
	.portaout({_led,ovl}),
	.kbdrst(kbdrst),
	.kbddat(kbddat),
	.kbdclk(kbdclk),
	.osdctrl(osdctrl)
);

//instantiate cia B
ciab ciab 
(
	.clk(clk),
	.aen(selciab),
	.rd(rd),
	.wr(hwr),
	.reset(reset),
	.rs(address[11:8]),
	.datain(data[15:8]),
	.dataout(ciadataout[15:8]),
	.tick(sol),//hsync count
	.e(e),
	.flag(indx),
	.irq(int6),
	.portain({1'b0,cts,1'b0}),
	.portaout({dtr,rts}),
	.portbout({_motor,_sel3,_sel2,_sel1,_sel0,side,direc,_step})
);


//instantiate cpu bridge
m68k_bridge M1 
(	
	.clk(clk),
	.qclk(qclk),
	.cen(cpuok),
	._as(_as),
	._lds(_lds),
	._uds(_uds),
	.r_w(r_w),
	._dtack(_dtack),
	.rd(cpurd),
	.hwr(cpuhwr),
	.lwr(cpulwr),
	.data(cpudata),
	.dataout(cpudataout),
	.datain(data)
);

//instantiate sram bridge
sram_bridge S1 
(
	.clk(clk),
	.qclk(qclk),
	.aen1((~ovr|~cpurd)&selchip&(~address[19])),//first 512Kbyte of chipram
	.aen2(selchip&address[19]&extra_chip | selslow&~extra_chip&extra_slow),//second 512Kbyte of chipram
	.aen3((selcart&aron) | (selslow&~aron&extra_chip&extra_slow)),//512Kbyte of slow ram or Action Replay ROM
	.aen4(selkick&(boot|rd)),//512Kbyte of kickstart rom (write enabled when boot asserted)
	.datain(data),
	.dataout(ramdataout),
	.rd(rd),
	.hwr(hwr),
	.lwr(lwr),
	._ub(_ub),
	._lb(_lb),
	._we(_we),
	._oe(_oe),
	._sel0(_ramsel0),
	._sel1(_ramsel1),
	.data(ramdata),
	.address19(ramaddress[19])
);

assign ramaddress[18:1] = address[18:1];

ActionReplay AR1
(	
	.clk(clk),
	.reset(reset),
	.cpuaddress(cpuaddress[23:1]),
	.regaddress(regaddress),
	.datain(data),
	.dataout(cartdataout),
	.cpurd(cpurd),
	.cpuhwr(cpuhwr),
	.cpulwr(cpulwr),
	.dma(dma),
	.boot(boot),
	.freeze(osdctrl[4]),
	.int7(int7),
	.ovr(ovr),
	.selmem(selcart),
	.aron(aron)
);

//level 7 interrupt for CPU
assign _ipl = int7 ? 3'b000 : _iplx;	//m68k interrupt request

//instantiate gary
gary G1 
(
	.clk(clk),
	.e(e),
	.cpuaddress(cpuaddress[23:12]),
	.cpurd(cpurd),
	.cpuhwr(cpuhwr),
	.cpulwr(cpulwr),
	.cpuok(cpuok),
	.dma(dma),
	.dmawr(dmawr),
	.dmapri(dmapri),
	.ovl(ovl),
	.boot(boot),
	.rd(rd),
	.hwr(hwr),
	.lwr(lwr),
	.selreg(selreg),
	.selchip(selchip),
	.selslow(selslow),
	.selciaa(selciaa),
	.selciab(selciab),
	.selkick(selkick),
	.selboot(selboot)	
);

//instantiate boot rom
bootrom R1 
(	
	.clk(clk),
	.aen(selboot),
	.rd(rd),
	.address(cpuaddress[10:1]),
	.dataout(bootdataout)	
);

//instantiate system control
syscontrol L1 
(	
	.clk(clk),
	.mrst(kbdrst|usrrst),
	.bootdone(selciaa&selciab),
	.reset(reset),
	.boot(boot),
	.bootrst(bootrst)
);

//instantiate clock generator
clock_generator C1
(	
	.mclk(mclk),
	.clk28m(clk28m),	//28.37516 MHz clock output
	.clk(clk),			//7.09379  MHz clock output
	.clk90(qclk),
	.e(e)
);

//-------------------------------------------------------------------------------------

//data multiplexer
assign data[15:0]=ramdataout[15:0]|cpudataout[15:0]|pauladataout[15:0]|userdataout|denisedataout[15:0]|bootdataout[15:0]|ciadataout[15:0]|agnusdataout[15:0]|cartdataout[15:0];

//--------------------------------------------------------------------------------------

//spi multiplexer
assign spidout=(!_spisel0 || !_spisel1) ? (paulaspidout|userspidout) : 1'bz;


//--------------------------------------------------------------------------------------

//cpu reset and clock
assign _cpureset=~reset;
assign cpuclk=~clk;


//--------------------------------------------------------------------------------------

endmodule

//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------

//syscontrol handles the startup of the FGPA,
//after fpga config, it automatically does a global system reset and asserts boot.
//the boot signal puts gary in a special mode so that the bootrom
//is mapped into the system memory map.	The firmware in the bootrom
//then loads the kickstart via the diskcontroller into the kickstart ram area.
//When kickstart has been loaded, the bootrom asserts bootdone by selecting both cia's at once. 
//This resets the system for a second time but it also de-asserts boot.
//Thus, the system now boots as a regular amiga.
//Subsequent resets by asserting mrst will not assert boot again.
//JB:
//2008-07-11	- reset to bootloader

module syscontrol
(
	input	clk,			//bus clock
	input	mrst,			//master/user reset input
	input	bootdone,		//bootrom program finished input
	output	reg reset,		//global synchronous system reset
	output	reg boot,		//bootrom overlay enable output
	input	bootrst			//reset to bootloader
);

//local signals
reg		smrst;					//registered input
reg		bootff=0;				//boot control SHOULD BE CLEARED BY CONFIG
reg		[23:0]rstcnt=24'h0;	//reset timer SHOULD BE CLEARED BY CONFIG

//asynchronous mrst input synchronizer (JB: hmmm, it seems that all reset inputs are synchronous)
always @(posedge clk)
	smrst <= mrst;

//reset timer and mrst control
always @(posedge clk)
	if(smrst || (boot && bootdone && rstcnt[23]))
		rstcnt <= 0;
	else if (!rstcnt[23])
		rstcnt <= rstcnt+1;

//boot control
always @(posedge clk)
	if (bootrst)
		bootff <= 0;
	else if (bootdone && rstcnt[23])
		bootff <= 1;

//global reset output
always @(posedge clk)
	reset <= ~rstcnt[23];

//boot output
always @(posedge clk)
	boot <= ~bootff;

endmodule

//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------

// This module interfaces the minimig's synchronous bus to the asynchronous sram
// on the Minimig rev1.0 board
module sram_bridge(clk,qclk,aen1,aen2,aen3,aen4,datain,dataout,rd,hwr,lwr,_ub,_lb,_we,_oe,_sel0,_sel1,data,address19);
input clk;				//bus clock
input qclk;				//quadrature bus clock
input aen1;				//bus adress enable	sram block 1
input aen2;				//bus adress enable	sram block 2
input aen3;				//bus adress enable	sram block 3
input aen4;				//bus adress enable	sram block 4
input [15:0] datain;	 	//bus data in
output [15:0] dataout;		//bus data out
input rd;			   		//bus read
input hwr;				//bus high write
input lwr;				//bus low write
output _ub;				//sram upper byte
output _lb;   				//sram lower byte
output _we;				//sram write enable
output _oe;    			//sram output enable
output _sel0;	  			//sram bank 0 enable
output _sel1;	  			//sram bank 1 enable
inout [15:0]data;	  		//sram data
output address19;			//sram address line 19	 

wire		enable;			// enable signal
reg		p1;	    			// used to time write and driver enable
reg		p2;				// used to time write and driver enable
reg		p3;				// used to time write and driver enable
wire		write;			// write pulse timing
wire		drive;			// output drive pulse timing
wire		t;				// output drive enable

// generate enable signal if we are adressed
assign enable=aen1|aen2|aen3|aen4;

// generate write pulse and data output drive pulse
always @(posedge clk)
	p1<=~p1;
always @(negedge clk)
	p2<=p1;
always @(negedge qclk)
	p3<=p1;
assign write=(p2^p3);
assign drive=~(p1^p2);

// generate _we
assign _we=~( write&enable&(hwr|lwr) ); 

//generate t
assign t=~( drive&enable&(hwr|lwr) );

// generate _oe
assign _oe=~( enable & rd );

// generate _ub
assign _ub=~( enable & (rd|hwr) );

// generate _lb
assign _lb=~( enable & (rd|lwr) );

// map aen1..aen4 to sram
// the sram is organized in 2 1MBbyte 16bit wide memory banks
// ean1..aen4 select 512kbyte	banks
assign _sel0=~(aen1|aen2);
assign _sel1=~(aen3|aen4);
assign address19=aen2|aen4;

// dataout multiplexer
assign dataout[15:0]=(enable && rd)?data[15:0]:16'b0000000000000000;

// data tristate buffers
assign data[15:0]=(t)?16'bz:datain[15:0];

endmodule

//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------

// This module interfaces the minimig's synchronous bus to the asynchronous 
// MC68SEC000 bus on the Minimig rev1.0 board
module m68k_bridge(clk,qclk,cen,_as,_lds,_uds,r_w,_dtack,rd,hwr,lwr,data,dataout,datain);
input clk;				// bus clock
input qclk;				// bus quadrature clock
input cen; 				// bus clock enable (dma slot for m68k bridge)
input _as;				// m68k adress strobe
input _lds;				// m68k lower data strobe d0-d7
input _uds;				// m68k upper data strobe d8-d15
input r_w;				// m68k read / write
output _dtack;				// m68k data acknowledge to cpu
output rd;				// bus read 
output hwr;				// bus high write
output lwr;				// bus low write
inout [15:0] data;			// m68k data
output [15:0] dataout;		// bus data out
input [15:0] datain;		// bus data in

reg		_dtack;			// see above
wire		t;				// bidirectional buffer control
reg		[15:0]ldatain;		// latched datain
reg		[15:0]ldataout;	// latched dataout
reg		enable;			// enable
reg 		[15:0]dataout;		// see output description
reg		rd,hwr,lwr;		// see output description
wire		l_as,l_lds,l_uds,lr_w,l_dtack;  // synchronised inputs
wire		valid;			// true if synchronised inputs are valid
reg		[4:0]latcha;
reg		[4:0]latchb;
reg		[9:0]latchc;

// latch input signals phase A
always @(negedge qclk)
begin
	latcha[0]<=_as;
	latcha[1]<=_lds;
	latcha[2]<=_uds;
	latcha[3]<=r_w;
	latcha[4]<=_dtack;
end

// latch input signals phase B
always @(posedge clk)
begin
	latchb[0]<=_as;
	latchb[1]<=_lds;
	latchb[2]<=_uds;
	latchb[3]<=r_w;
	latchb[4]<=_dtack;
end

// latch input signals phase C
always @(posedge qclk)
	latchc[9:0]<={latchb[4:0],latcha[4:0]};

// generate synchronised signals and valid signal
assign valid=(latchc[9:5]==latchc[4:0])?1:0;
assign l_as=latchc[5];
assign l_lds=latchc[6];
assign l_uds=latchc[7];
assign lr_w=latchc[8];
assign l_dtack=latchc[9];	

// generate rd,hwr,lwr and enable
always @(valid or l_as or l_lds or l_uds or lr_w or l_dtack or cen)
begin
	// normal cpu cycle
	if(valid && cen && !l_as && l_dtack && (!l_uds || !l_lds))
	begin
		if(lr_w)
		begin// 16bit read cycle
			enable=1;
			rd=1;
			hwr=0;
			lwr=0;			
		end
		else
		begin// 16bit or 8bit write cycle
			rd=0;
			enable=1;
			if(!l_uds)
				hwr=1;
			else
				hwr=0;
			if(!l_lds)
				lwr=1;
			else
				lwr=0;
		end
	end
	else
	begin// IDLE cycle
		enable=0;
		rd=0;
		hwr=0;
		lwr=0;	
	end
end


// generate t
assign t=(~r_w) | (_lds&_uds);

// dtack control
always @(negedge clk)
	if(l_as && valid)
		_dtack<=1;
	else if(enable)
		_dtack<=0;

//--------------------------------------------------------------------------------------

// dataout multiplexer and latch 
always @(posedge clk)
	ldataout<=data;	  
always @(hwr or lwr or ldataout)
	if(hwr || lwr)
		dataout=ldataout;
	else
		dataout=16'b0000000000000000;

// datain latch
always @(posedge clk)
	if(enable)
		ldatain<=datain;

//--------------------------------------------------------------------------------------

// data tristate buffers
assign data[15:0]=(t)?16'bz:ldatain[15:0];

endmodule