vending_machine.tan.qmsg

自动售货机模型

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "choose register register item\[0\] item\[1\] 200.0 MHz Internal " "Info: Clock \"choose\" Internal fmax is restricted to 200.0 MHz between source register \"item\[0\]\" and destination register \"item\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns item\[0\] 1 REG LC6_E5 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_E5; Fanout = 14; REG Node = 'item\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { item[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 1.400 ns item\[1\] 2 REG LC8_E5 21 " "Info: 2: + IC(0.200 ns) + CELL(1.200 ns) = 1.400 ns; Loc. = LC8_E5; Fanout = 21; REG Node = 'item\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { item[0] item[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 85.71 % ) " "Info: Total cell delay = 1.200 ns ( 85.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 14.29 % ) " "Info: Total interconnect delay = 0.200 ns ( 14.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { item[0] item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { item[0] {} item[1] {} } { 0.000ns 0.200ns } { 0.000ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "choose destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"choose\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns choose 1 CLK PIN_183 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 2; CLK Node = 'choose'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { choose } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns item\[1\] 2 REG LC8_E5 21 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_E5; Fanout = 21; REG Node = 'item\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { choose item[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { choose item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { choose {} choose~out {} item[1] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "choose source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"choose\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns choose 1 CLK PIN_183 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 2; CLK Node = 'choose'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { choose } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns item\[0\] 2 REG LC6_E5 14 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_E5; Fanout = 14; REG Node = 'item\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { choose item[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { choose item[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { choose {} choose~out {} item[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { choose item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { choose {} choose~out {} item[1] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { choose item[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { choose {} choose~out {} item[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { item[0] item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { item[0] {} item[1] {} } { 0.000ns 0.200ns } { 0.000ns 1.200ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { choose item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { choose {} choose~out {} item[1] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { choose item[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { choose {} choose~out {} item[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { item[1] {} } {  } {  } "" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "purchase register register purchase_status\[0\] purchase_status\[0\] 200.0 MHz Internal " "Info: Clock \"purchase\" Internal fmax is restricted to 200.0 MHz between source register \"purchase_status\[0\]\" and destination register \"purchase_status\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.200 ns + Longest register register " "Info: + Longest register to register delay is 1.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns purchase_status\[0\] 1 REG LC1_E9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E9; Fanout = 6; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 1.200 ns purchase_status\[0\] 2 REG LC1_E9 6 " "Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 1.200 ns; Loc. = LC1_E9; Fanout = 6; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { purchase_status[0] purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 83.33 % ) " "Info: Total cell delay = 1.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.200 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { purchase_status[0] purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.200 ns" { purchase_status[0] {} purchase_status[0] {} } { 0.000ns 0.200ns } { 0.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "purchase destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"purchase\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns purchase 1 CLK PIN_184 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 1; CLK Node = 'purchase'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns purchase_status\[0\] 2 REG LC1_E9 6 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_E9; Fanout = 6; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { purchase {} purchase~out {} purchase_status[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "purchase source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"purchase\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns purchase 1 CLK PIN_184 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 1; CLK Node = 'purchase'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns purchase_status\[0\] 2 REG LC1_E9 6 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_E9; Fanout = 6; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { purchase {} purchase~out {} purchase_status[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { purchase {} purchase~out {} purchase_status[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { purchase {} purchase~out {} purchase_status[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { purchase_status[0] purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.200 ns" { purchase_status[0] {} purchase_status[0] {} } { 0.000ns 0.200ns } { 0.000ns 1.000ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { purchase {} purchase~out {} purchase_status[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { purchase {} purchase~out {} purchase_status[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { purchase_status[0] {} } {  } {  } "" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "ram_store~37 quantity\[2\] clk 8.000 ns register " "Info: tsu for register \"ram_store~37\" (data pin = \"quantity\[2\]\", clock pin = \"clk\") is 8.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.200 ns + Longest pin register " "Info: + Longest pin to register delay is 9.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns quantity\[2\] 1 PIN PIN_176 5 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_176; Fanout = 5; PIN Node = 'quantity\[2\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { quantity[2] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.500 ns) 9.200 ns ram_store~37 2 REG LC3_L24 2 " "Info: 2: + IC(4.600 ns) + CELL(1.500 ns) = 9.200 ns; Loc. = LC3_L24; Fanout = 2; REG Node = 'ram_store~37'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { quantity[2] ram_store~37 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 50.00 % ) " "Info: Total cell delay = 4.600 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 50.00 % ) " "Info: Total interconnect delay = 4.600 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "9.200 ns" { quantity[2] ram_store~37 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "9.200 ns" { quantity[2] {} quantity[2]~out {} ram_store~37 {} } { 0.000ns 0.000ns 4.600ns } { 0.000ns 3.100ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns ram_store~37 2 REG LC3_L24 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_L24; Fanout = 2; REG Node = 'ram_store~37'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk ram_store~37 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk ram_store~37 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} ram_store~37 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "9.200 ns" { quantity[2] ram_store~37 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "9.200 ns" { quantity[2] {} quantity[2]~out {} ram_store~37 {} } { 0.000ns 0.000ns 4.600ns } { 0.000ns 3.100ns 1.500ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk ram_store~37 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} ram_store~37 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk show_price_data\[3\] buyer_money\[3\] 31.000 ns register " "Info: tco from clock \"clk\" to destination pin \"show_price_data\[3\]\" through register \"buyer_money\[3\]\" is 31.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns insert_dollar 2 REG LC1_E23 4 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_E23; Fanout = 4; REG Node = 'insert_dollar'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk insert_dollar } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(0.000 ns) 7.900 ns buyer_money\[3\] 3 REG LC5_E3 6 " "Info: 3: + IC(4.900 ns) + CELL(0.000 ns) = 7.900 ns; Loc. = LC5_E3; Fanout = 6; REG Node = 'buyer_money\[3\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { insert_dollar buyer_money[3] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 20.25 % ) " "Info: Total cell delay = 1.600 ns ( 20.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns ( 79.75 % ) " "Info: Total interconnect delay = 6.300 ns ( 79.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk insert_dollar buyer_money[3] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} insert_dollar {} buyer_money[3] {} } { 0.000ns 0.000ns 1.400ns 4.900ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns + Longest register pin " "Info: + Longest register to pin delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buyer_money\[3\] 1 REG LC5_E3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_E3; Fanout = 6; REG Node = 'buyer_money\[3\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { buyer_money[3] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.000 ns) 3.000 ns money\[3\]~10 2 COMB LC1_E2 1 " "Info: 2: + IC(1.000 ns) + CELL(2.000 ns) = 3.000 ns; Loc. = LC1_E2; Fanout = 1; COMB Node = 'money\[3\]~10'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { buyer_money[3] money[3]~10 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.900 ns) 7.200 ns money\[3\]~11 3 COMB LC3_E16 7 " "Info: 3: + IC(2.300 ns) + CELL(1.900 ns) = 7.200 ns; Loc. = LC3_E16; Fanout = 7; COMB Node = 'money\[3\]~11'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.200 ns" { money[3]~10 money[3]~11 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.700 ns) 10.700 ns Mux10~0 4 COMB LC7_E14 1 " "Info: 4: + IC(1.800 ns) + CELL(1.700 ns) = 10.700 ns; Loc. = LC7_E14; Fanout = 1; COMB Node = 'Mux10~0'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { money[3]~11 Mux10~0 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(8.600 ns) 22.000 ns show_price_data\[3\] 5 PIN PIN_125 0 " "Info: 5: + IC(2.700 ns) + CELL(8.600 ns) = 22.000 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'show_price_data\[3\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "11.300 ns" { Mux10~0 show_price_data[3] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.200 ns ( 64.55 % ) " "Info: Total cell delay = 14.200 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.800 ns ( 35.45 % ) " "Info: Total interconnect delay = 7.800 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { buyer_money[3] money[3]~10 money[3]~11 Mux10~0 show_price_data[3] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { buyer_money[3] {} money[3]~10 {} money[3]~11 {} Mux10~0 {} show_price_data[3] {} } { 0.000ns 1.000ns 2.300ns 1.800ns 2.700ns } { 0.000ns 2.000ns 1.900ns 1.700ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk insert_dollar buyer_money[3] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} insert_dollar {} buyer_money[3] {} } { 0.000ns 0.000ns 1.400ns 4.900ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { buyer_money[3] money[3]~10 money[3]~11 Mux10~0 show_price_data[3] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { buyer_money[3] {} money[3]~10 {} money[3]~11 {} Mux10~0 {} show_price_data[3] {} } { 0.000ns 1.000ns 2.300ns 1.800ns 2.700ns } { 0.000ns 2.000ns 1.900ns 1.700ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}