vending_machine.tan.qmsg

自动售货机模型

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "choose " "Info: Assuming node \"choose\" is an undefined clock" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "choose" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "purchase " "Info: Assuming node \"purchase\" is an undefined clock" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "purchase" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "insert_dollar " "Info: Detected ripple clock \"insert_dollar\" as buffer" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 28 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "insert_dollar" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register buyer_money\[2\] register back_money\[2\] 68.97 MHz 14.5 ns Internal " "Info: Clock \"clk\" has Internal fmax of 68.97 MHz between source register \"buyer_money\[2\]\" and destination register \"back_money\[2\]\" (period= 14.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Longest register register " "Info: + Longest register to register delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buyer_money\[2\] 1 REG LC4_E3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_E3; Fanout = 8; REG Node = 'buyer_money\[2\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { buyer_money[2] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 2.100 ns merchandise_out~2 2 COMB LC1_E3 1 " "Info: 2: + IC(0.200 ns) + CELL(1.900 ns) = 2.100 ns; Loc. = LC1_E3; Fanout = 1; COMB Node = 'merchandise_out~2'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { buyer_money[2] merchandise_out~2 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.200 ns) 5.300 ns merchandise_out~5 3 COMB LC8_E1 5 " "Info: 3: + IC(1.000 ns) + CELL(2.200 ns) = 5.300 ns; Loc. = LC8_E1; Fanout = 5; COMB Node = 'merchandise_out~5'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { merchandise_out~2 merchandise_out~5 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 6.700 ns back_money\[2\] 4 REG LC1_E1 3 " "Info: 4: + IC(0.200 ns) + CELL(1.200 ns) = 6.700 ns; Loc. = LC1_E1; Fanout = 3; REG Node = 'back_money\[2\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { merchandise_out~5 back_money[2] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 79.10 % ) " "Info: Total cell delay = 5.300 ns ( 79.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 20.90 % ) " "Info: Total interconnect delay = 1.400 ns ( 20.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { buyer_money[2] merchandise_out~2 merchandise_out~5 back_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "6.700 ns" { buyer_money[2] {} merchandise_out~2 {} merchandise_out~5 {} back_money[2] {} } { 0.000ns 0.200ns 1.000ns 0.200ns } { 0.000ns 1.900ns 2.200ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.000 ns - Smallest " "Info: - Smallest clock skew is -6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns back_money\[2\] 2 REG LC1_E1 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_E1; Fanout = 3; REG Node = 'back_money\[2\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk back_money[2] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk back_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} back_money[2] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns insert_dollar 2 REG LC1_E23 4 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_E23; Fanout = 4; REG Node = 'insert_dollar'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk insert_dollar } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(0.000 ns) 7.900 ns buyer_money\[2\] 3 REG LC4_E3 8 " "Info: 3: + IC(4.900 ns) + CELL(0.000 ns) = 7.900 ns; Loc. = LC4_E3; Fanout = 8; REG Node = 'buyer_money\[2\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { insert_dollar buyer_money[2] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 20.25 % ) " "Info: Total cell delay = 1.600 ns ( 20.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns ( 79.75 % ) " "Info: Total interconnect delay = 6.300 ns ( 79.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk insert_dollar buyer_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} insert_dollar {} buyer_money[2] {} } { 0.000ns 0.000ns 1.400ns 4.900ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk back_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} back_money[2] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk insert_dollar buyer_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} insert_dollar {} buyer_money[2] {} } { 0.000ns 0.000ns 1.400ns 4.900ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { buyer_money[2] merchandise_out~2 merchandise_out~5 back_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "6.700 ns" { buyer_money[2] {} merchandise_out~2 {} merchandise_out~5 {} back_money[2] {} } { 0.000ns 0.200ns 1.000ns 0.200ns } { 0.000ns 1.900ns 2.200ns 1.200ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk back_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} back_money[2] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk insert_dollar buyer_money[2] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} insert_dollar {} buyer_money[2] {} } { 0.000ns 0.000ns 1.400ns 4.900ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}