prev_cmp_vending_machine.tan.qmsg

自动售货机模型

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "purchase register register purchase_status\[0\] purchase_status\[0\] 275.03 MHz Internal " "Info: Clock \"purchase\" Internal fmax is restricted to 275.03 MHz between source register \"purchase_status\[0\]\" and destination register \"purchase_status\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.906 ns + Longest register register " "Info: + Longest register to register delay is 0.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns purchase_status\[0\] 1 REG LC_X8_Y11_N0 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y11_N0; Fanout = 7; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.597 ns) + CELL(0.309 ns) 0.906 ns purchase_status\[0\] 2 REG LC_X8_Y11_N0 7 " "Info: 2: + IC(0.597 ns) + CELL(0.309 ns) = 0.906 ns; Loc. = LC_X8_Y11_N0; Fanout = 7; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.906 ns" { purchase_status[0] purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 34.11 % ) " "Info: Total cell delay = 0.309 ns ( 34.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.597 ns ( 65.89 % ) " "Info: Total interconnect delay = 0.597 ns ( 65.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.906 ns" { purchase_status[0] purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "0.906 ns" { purchase_status[0] {} purchase_status[0] {} } { 0.000ns 0.597ns } { 0.000ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "purchase destination 3.737 ns + Shortest register " "Info: + Shortest clock path from clock \"purchase\" to destination register is 3.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns purchase 1 CLK PIN_6 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 1; CLK Node = 'purchase'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.711 ns) 3.737 ns purchase_status\[0\] 2 REG LC_X8_Y11_N0 7 " "Info: 2: + IC(1.557 ns) + CELL(0.711 ns) = 3.737 ns; Loc. = LC_X8_Y11_N0; Fanout = 7; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.268 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 58.34 % ) " "Info: Total cell delay = 2.180 ns ( 58.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.557 ns ( 41.66 % ) " "Info: Total interconnect delay = 1.557 ns ( 41.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.737 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "3.737 ns" { purchase {} purchase~out0 {} purchase_status[0] {} } { 0.000ns 0.000ns 1.557ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "purchase source 3.737 ns - Longest register " "Info: - Longest clock path from clock \"purchase\" to source register is 3.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns purchase 1 CLK PIN_6 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 1; CLK Node = 'purchase'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.711 ns) 3.737 ns purchase_status\[0\] 2 REG LC_X8_Y11_N0 7 " "Info: 2: + IC(1.557 ns) + CELL(0.711 ns) = 3.737 ns; Loc. = LC_X8_Y11_N0; Fanout = 7; REG Node = 'purchase_status\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.268 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 58.34 % ) " "Info: Total cell delay = 2.180 ns ( 58.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.557 ns ( 41.66 % ) " "Info: Total interconnect delay = 1.557 ns ( 41.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.737 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "3.737 ns" { purchase {} purchase~out0 {} purchase_status[0] {} } { 0.000ns 0.000ns 1.557ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.737 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "3.737 ns" { purchase {} purchase~out0 {} purchase_status[0] {} } { 0.000ns 0.000ns 1.557ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.906 ns" { purchase_status[0] purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "0.906 ns" { purchase_status[0] {} purchase_status[0] {} } { 0.000ns 0.597ns } { 0.000ns 0.309ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.737 ns" { purchase purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "3.737 ns" { purchase {} purchase~out0 {} purchase_status[0] {} } { 0.000ns 0.000ns 1.557ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { purchase_status[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { purchase_status[0] {} } {  } {  } "" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 29 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "choose register register item\[0\] item\[1\] 275.03 MHz Internal " "Info: Clock \"choose\" Internal fmax is restricted to 275.03 MHz between source register \"item\[0\]\" and destination register \"item\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.125 ns + Longest register register " "Info: + Longest register to register delay is 1.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns item\[0\] 1 REG LC_X21_Y8_N3 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y8_N3; Fanout = 21; REG Node = 'item\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { item[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.607 ns) 1.125 ns item\[1\] 2 REG LC_X21_Y8_N0 22 " "Info: 2: + IC(0.518 ns) + CELL(0.607 ns) = 1.125 ns; Loc. = LC_X21_Y8_N0; Fanout = 22; REG Node = 'item\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { item[0] item[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 53.96 % ) " "Info: Total cell delay = 0.607 ns ( 53.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.518 ns ( 46.04 % ) " "Info: Total interconnect delay = 0.518 ns ( 46.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { item[0] item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.125 ns" { item[0] {} item[1] {} } { 0.000ns 0.518ns } { 0.000ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "choose destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"choose\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns choose 1 CLK PIN_16 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 2; CLK Node = 'choose'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { choose } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns item\[1\] 2 REG LC_X21_Y8_N0 22 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X21_Y8_N0; Fanout = 22; REG Node = 'item\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { choose item[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { choose item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { choose {} choose~out0 {} item[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "choose source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"choose\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns choose 1 CLK PIN_16 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 2; CLK Node = 'choose'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { choose } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns item\[0\] 2 REG LC_X21_Y8_N3 21 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X21_Y8_N3; Fanout = 21; REG Node = 'item\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { choose item[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { choose item[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { choose {} choose~out0 {} item[0] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { choose item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { choose {} choose~out0 {} item[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { choose item[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { choose {} choose~out0 {} item[0] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { item[0] item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "1.125 ns" { item[0] {} item[1] {} } { 0.000ns 0.518ns } { 0.000ns 0.607ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { choose item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { choose {} choose~out0 {} item[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { choose item[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { choose {} choose~out0 {} item[0] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { item[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { item[1] {} } {  } {  } "" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 53 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "ram_store~14 set_init clk 8.172 ns register " "Info: tsu for register \"ram_store~14\" (data pin = \"set_init\", clock pin = \"clk\") is 8.172 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.917 ns + Longest pin register " "Info: + Longest pin to register delay is 10.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns set_init 1 PIN PIN_130 22 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_130; Fanout = 22; PIN Node = 'set_init'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { set_init } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.563 ns) + CELL(0.442 ns) 8.480 ns ram_store~61 2 COMB LC_X21_Y9_N4 8 " "Info: 2: + IC(6.563 ns) + CELL(0.442 ns) = 8.480 ns; Loc. = LC_X21_Y9_N4; Fanout = 8; COMB Node = 'ram_store~61'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.005 ns" { set_init ram_store~61 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.867 ns) 10.917 ns ram_store~14 3 REG LC_X19_Y8_N2 1 " "Info: 3: + IC(1.570 ns) + CELL(0.867 ns) = 10.917 ns; Loc. = LC_X19_Y8_N2; Fanout = 1; REG Node = 'ram_store~14'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.437 ns" { ram_store~61 ram_store~14 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 25.50 % ) " "Info: Total cell delay = 2.784 ns ( 25.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.133 ns ( 74.50 % ) " "Info: Total interconnect delay = 8.133 ns ( 74.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "10.917 ns" { set_init ram_store~61 ram_store~14 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "10.917 ns" { set_init {} set_init~out0 {} ram_store~61 {} ram_store~14 {} } { 0.000ns 0.000ns 6.563ns 1.570ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ram_store~14 2 REG LC_X19_Y8_N2 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X19_Y8_N2; Fanout = 1; REG Node = 'ram_store~14'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk ram_store~14 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ram_store~14 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} ram_store~14 {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "10.917 ns" { set_init ram_store~61 ram_store~14 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "10.917 ns" { set_init {} set_init~out0 {} ram_store~61 {} ram_store~14 {} } { 0.000ns 0.000ns 6.563ns 1.570ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ram_store~14 } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} ram_store~14 {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}