prev_cmp_vending_machine.tan.qmsg

自动售货机模型

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "purchase " "Info: Assuming node \"purchase\" is an undefined clock" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "purchase" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "choose " "Info: Assuming node \"choose\" is an undefined clock" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "choose" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "insert_dollar " "Info: Detected ripple clock \"insert_dollar\" as buffer" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 28 -1 0 } } { "d:/program files/alter/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/quartus/bin/Assignment Editor.qase" 1 { { 0 "insert_dollar" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register buyer_money\[1\] register back_money\[0\] 118.36 MHz 8.449 ns Internal " "Info: Clock \"clk\" has Internal fmax of 118.36 MHz between source register \"buyer_money\[1\]\" and destination register \"back_money\[0\]\" (period= 8.449 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.242 ns + Longest register register " "Info: + Longest register to register delay is 3.242 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buyer_money\[1\] 1 REG LC_X8_Y9_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y9_N2; Fanout = 10; REG Node = 'buyer_money\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { buyer_money[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.292 ns) 1.082 ns merchandise_out~1 2 COMB LC_X7_Y9_N2 1 " "Info: 2: + IC(0.790 ns) + CELL(0.292 ns) = 1.082 ns; Loc. = LC_X7_Y9_N2; Fanout = 1; COMB Node = 'merchandise_out~1'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.082 ns" { buyer_money[1] merchandise_out~1 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.378 ns merchandise_out~2 3 COMB LC_X7_Y9_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.378 ns; Loc. = LC_X7_Y9_N3; Fanout = 1; COMB Node = 'merchandise_out~2'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { merchandise_out~1 merchandise_out~2 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.674 ns merchandise_out~3 4 COMB LC_X7_Y9_N4 5 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 1.674 ns; Loc. = LC_X7_Y9_N4; Fanout = 5; COMB Node = 'merchandise_out~3'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { merchandise_out~2 merchandise_out~3 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(1.112 ns) 3.242 ns back_money\[0\] 5 REG LC_X7_Y9_N6 1 " "Info: 5: + IC(0.456 ns) + CELL(1.112 ns) = 3.242 ns; Loc. = LC_X7_Y9_N6; Fanout = 1; REG Node = 'back_money\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { merchandise_out~3 back_money[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.632 ns ( 50.34 % ) " "Info: Total cell delay = 1.632 ns ( 50.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.610 ns ( 49.66 % ) " "Info: Total interconnect delay = 1.610 ns ( 49.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.242 ns" { buyer_money[1] merchandise_out~1 merchandise_out~2 merchandise_out~3 back_money[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "3.242 ns" { buyer_money[1] {} merchandise_out~1 {} merchandise_out~2 {} merchandise_out~3 {} back_money[0] {} } { 0.000ns 0.790ns 0.182ns 0.182ns 0.456ns } { 0.000ns 0.292ns 0.114ns 0.114ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.946 ns - Smallest " "Info: - Smallest clock skew is -4.946 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.768 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns back_money\[0\] 2 REG LC_X7_Y9_N6 1 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X7_Y9_N6; Fanout = 1; REG Node = 'back_money\[0\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk back_money[0] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk back_money[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} back_money[0] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.714 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.714 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.935 ns) 2.992 ns insert_dollar 2 REG LC_X8_Y9_N7 4 " "Info: 2: + IC(0.588 ns) + CELL(0.935 ns) = 2.992 ns; Loc. = LC_X8_Y9_N7; Fanout = 4; REG Node = 'insert_dollar'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { clk insert_dollar } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.011 ns) + CELL(0.711 ns) 7.714 ns buyer_money\[1\] 3 REG LC_X8_Y9_N2 10 " "Info: 3: + IC(4.011 ns) + CELL(0.711 ns) = 7.714 ns; Loc. = LC_X8_Y9_N2; Fanout = 10; REG Node = 'buyer_money\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.722 ns" { insert_dollar buyer_money[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.38 % ) " "Info: Total cell delay = 3.115 ns ( 40.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.599 ns ( 59.62 % ) " "Info: Total interconnect delay = 4.599 ns ( 59.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.714 ns" { clk insert_dollar buyer_money[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.714 ns" { clk {} clk~out0 {} insert_dollar {} buyer_money[1] {} } { 0.000ns 0.000ns 0.588ns 4.011ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk back_money[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} back_money[0] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.714 ns" { clk insert_dollar buyer_money[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.714 ns" { clk {} clk~out0 {} insert_dollar {} buyer_money[1] {} } { 0.000ns 0.000ns 0.588ns 4.011ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.242 ns" { buyer_money[1] merchandise_out~1 merchandise_out~2 merchandise_out~3 back_money[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "3.242 ns" { buyer_money[1] {} merchandise_out~1 {} merchandise_out~2 {} merchandise_out~3 {} back_money[0] {} } { 0.000ns 0.790ns 0.182ns 0.182ns 0.456ns } { 0.000ns 0.292ns 0.114ns 0.114ns 1.112ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk back_money[0] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} back_money[0] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "7.714 ns" { clk insert_dollar buyer_money[1] } "NODE_NAME" } } { "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/alter/quartus/bin/Technology_Viewer.qrui" "7.714 ns" { clk {} clk~out0 {} insert_dollar {} buyer_money[1] {} } { 0.000ns 0.000ns 0.588ns 4.011ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}