prev_cmp_vending_machine.fit.qmsg

自动售货机模型

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register buyer_money\[1\] register merchandise_out~reg0 -7.97 ns " "Info: Slack time is -7.97 ns between source register \"buyer_money\[1\]\" and destination register \"merchandise_out~reg0\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-4.151 ns + Largest register register " "Info: + Largest register to register requirement is -4.151 ns" {  } {  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.753 ns   Shortest register " "Info:   Shortest clock path from clock \"clk\" to destination register is 2.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.711 ns) 2.753 ns merchandise_out~reg0 2 REG Unassigned 2 " "Info: 2: + IC(0.573 ns) + CELL(0.711 ns) = 2.753 ns; Loc. = Unassigned; Fanout = 2; REG Node = 'merchandise_out~reg0'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { clk merchandise_out~reg0 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 111 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.19 % ) " "Info: Total cell delay = 2.180 ns ( 79.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.573 ns ( 20.81 % ) " "Info: Total interconnect delay = 0.573 ns ( 20.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.753 ns   Longest register " "Info:   Longest clock path from clock \"clk\" to destination register is 2.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.711 ns) 2.753 ns merchandise_out~reg0 2 REG Unassigned 2 " "Info: 2: + IC(0.573 ns) + CELL(0.711 ns) = 2.753 ns; Loc. = Unassigned; Fanout = 2; REG Node = 'merchandise_out~reg0'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { clk merchandise_out~reg0 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 111 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.19 % ) " "Info: Total cell delay = 2.180 ns ( 79.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.573 ns ( 20.81 % ) " "Info: Total interconnect delay = 0.573 ns ( 20.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.643 ns   Shortest register " "Info:   Shortest clock path from clock \"clk\" to source register is 7.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.935 ns) 2.977 ns insert_dollar 2 REG Unassigned 4 " "Info: 2: + IC(0.573 ns) + CELL(0.935 ns) = 2.977 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'insert_dollar'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { clk insert_dollar } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.955 ns) + CELL(0.711 ns) 7.643 ns buyer_money\[1\] 3 REG Unassigned 10 " "Info: 3: + IC(3.955 ns) + CELL(0.711 ns) = 7.643 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'buyer_money\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.666 ns" { insert_dollar buyer_money[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.76 % ) " "Info: Total cell delay = 3.115 ns ( 40.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.528 ns ( 59.24 % ) " "Info: Total interconnect delay = 4.528 ns ( 59.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.643 ns   Longest register " "Info:   Longest clock path from clock \"clk\" to source register is 7.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.935 ns) 2.977 ns insert_dollar 2 REG Unassigned 4 " "Info: 2: + IC(0.573 ns) + CELL(0.935 ns) = 2.977 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'insert_dollar'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { clk insert_dollar } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.955 ns) + CELL(0.711 ns) 7.643 ns buyer_money\[1\] 3 REG Unassigned 10 " "Info: 3: + IC(3.955 ns) + CELL(0.711 ns) = 7.643 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'buyer_money\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "4.666 ns" { insert_dollar buyer_money[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.76 % ) " "Info: Total cell delay = 3.115 ns ( 40.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.528 ns ( 59.24 % ) " "Info: Total interconnect delay = 4.528 ns ( 59.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 9 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns   " "Info:   Micro clock to output delay of source is 0.224 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns   " "Info:   Micro setup delay of destination is 0.037 ns" {  } { { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 111 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.819 ns - Longest register register " "Info: - Longest register to register delay is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buyer_money\[1\] 1 REG Unassigned 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 10; REG Node = 'buyer_money\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { buyer_money[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.114 ns) 0.969 ns merchandise_out~1 2 COMB Unassigned 1 " "Info: 2: + IC(0.855 ns) + CELL(0.114 ns) = 0.969 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'merchandise_out~1'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.969 ns" { buyer_money[1] merchandise_out~1 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.292 ns) 1.623 ns merchandise_out~2 3 COMB Unassigned 1 " "Info: 3: + IC(0.362 ns) + CELL(0.292 ns) = 1.623 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'merchandise_out~2'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { merchandise_out~1 merchandise_out~2 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.114 ns) 2.277 ns merchandise_out~3 4 COMB Unassigned 5 " "Info: 4: + IC(0.540 ns) + CELL(0.114 ns) = 2.277 ns; Loc. = Unassigned; Fanout = 5; COMB Node = 'merchandise_out~3'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { merchandise_out~2 merchandise_out~3 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.309 ns) 3.819 ns merchandise_out~reg0 5 REG Unassigned 2 " "Info: 5: + IC(1.233 ns) + CELL(0.309 ns) = 3.819 ns; Loc. = Unassigned; Fanout = 2; REG Node = 'merchandise_out~reg0'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { merchandise_out~3 merchandise_out~reg0 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 111 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.829 ns ( 21.71 % ) " "Info: Total cell delay = 0.829 ns ( 21.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.990 ns ( 78.29 % ) " "Info: Total interconnect delay = 2.990 ns ( 78.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { buyer_money[1] merchandise_out~1 merchandise_out~2 merchandise_out~3 merchandise_out~reg0 } "NODE_NAME" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { buyer_money[1] merchandise_out~1 merchandise_out~2 merchandise_out~3 merchandise_out~reg0 } "NODE_NAME" } }  } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.819 ns register register " "Info: Estimated most critical path is register to register delay of 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buyer_money\[1\] 1 REG LAB_X8_Y9 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y9; Fanout = 10; REG Node = 'buyer_money\[1\]'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "" { buyer_money[1] } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.114 ns) 0.969 ns merchandise_out~1 2 COMB LAB_X7_Y9 1 " "Info: 2: + IC(0.855 ns) + CELL(0.114 ns) = 0.969 ns; Loc. = LAB_X7_Y9; Fanout = 1; COMB Node = 'merchandise_out~1'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.969 ns" { buyer_money[1] merchandise_out~1 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.292 ns) 1.623 ns merchandise_out~2 3 COMB LAB_X7_Y9 1 " "Info: 3: + IC(0.362 ns) + CELL(0.292 ns) = 1.623 ns; Loc. = LAB_X7_Y9; Fanout = 1; COMB Node = 'merchandise_out~2'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { merchandise_out~1 merchandise_out~2 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.114 ns) 2.277 ns merchandise_out~3 4 COMB LAB_X7_Y9 5 " "Info: 4: + IC(0.540 ns) + CELL(0.114 ns) = 2.277 ns; Loc. = LAB_X7_Y9; Fanout = 5; COMB Node = 'merchandise_out~3'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { merchandise_out~2 merchandise_out~3 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.309 ns) 3.819 ns merchandise_out~reg0 5 REG LAB_X6_Y10 2 " "Info: 5: + IC(1.233 ns) + CELL(0.309 ns) = 3.819 ns; Loc. = LAB_X6_Y10; Fanout = 2; REG Node = 'merchandise_out~reg0'" {  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { merchandise_out~3 merchandise_out~reg0 } "NODE_NAME" } } { "vending_machine.vhd" "" { Text "D:/myproject/quarter/vending machine/vending_machine.vhd" 111 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.829 ns ( 21.71 % ) " "Info: Total cell delay = 0.829 ns ( 21.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.990 ns ( 78.29 % ) " "Info: Total interconnect delay = 2.990 ns ( 78.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/alter/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { buyer_money[1] merchandise_out~1 merchandise_out~2 merchandise_out~3 merchandise_out~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X0_Y0 X13_Y14 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}