16×4bit的fifo设计.txt

16×4bit的FIFO设计代码

16×4bit的FIFO设计。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fifo2 IS
  PORT(
        datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        dataout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        clk,reset,wr,rd:IN STD_LOGIC;
        full,empty : OUT STD_LOGIC);
END ENTITY fifo2;

ARCHITECTURE arc1 OF fifo2 IS

  SUBTYPE RAM_WORD IS STD_LOGIC_VECTOR(3 DOWNTO 0);
  SUBTYPE RAM_RANGE  IS INTEGER RANGE 0 TO 15;
  TYPE RAM_TYPE IS ARRAY(RAM_RANGE) OF RAM_WORD;
  SIGNAL myfifo: RAM_TYPE;  
  SIGNAL wp,rp:INTEGER RANGE 0 TO 15; 
  SIGNAL in_full,in_empty:STD_LOGIC;

  BEGIN
       full<=in_full;
       empty<=in_empty;
       dataout<=myfifo(rp);

     PROCESS(clk)        --data in stack
        BEGIN
          IF clk'EVENT AND clk='1' THEN 
               IF (wr='0' AND in_full='0')  THEN
                 myfifo(wp)<=datain; 
               END IF;
           END IF;
     END PROCESS;  

   PROCESS(clk,reset)        --wp modification
        BEGIN
          IF reset='1' THEN
             wp<=0; 
          ELSIF (clk'EVENT AND clk='1') THEN 
               IF (wp=0 AND in_full='0')  THEN
                 IF(wp=15) THEN
                    wp<=0;
                 ELSE  
                    wp<=wp+1;
                 END IF;
               END IF;
          END IF;
     END PROCESS;

   PROCESS(clk,reset)        --rp modification
        BEGIN
          IF (reset='1') THEN
             rp<=15; 
          ELSIF (clk'EVENT AND clk='1') THEN 
               IF (rd='0' AND in_empty='0')  THEN
                 IF(rp=15) THEN
                    rp<=0;
                 ELSE  
                    rp<=rp+1;
                 END IF;
               END IF;
          END IF;
     END PROCESS;

 PROCESS(clk,reset)        --empty flag
        BEGIN
          IF reset='1' THEN
             in_empty<='1'; 
          ELSIF (clk'EVENT AND clk='1') THEN 
               IF (      (rp=wp-2  OR (rp=15 AND wp=1) OR (rp=14 AND wp=0))
                    AND  (rd='0' and wr='1')  )  THEN
                      in_empty<='1';
               ELSIF(in_empty='1' AND wr='0') THEN
                     in_empty<='0';  
               END IF;
          END IF;
    END PROCESS;

 PROCESS(clk,reset)        --full flag
        BEGIN
          IF reset='1' THEN
             in_full<='0'; 
          ELSIF (clk'EVENT AND clk='1') THEN 
               IF (     rp=wp AND wr='0' AND rd='1')  THEN
                       in_full<='1'; 
               ELSIF(in_full='1' AND rd='0') THEN
                     in_full<='0';  
               END IF;
          END IF;
    END PROCESS;

END ARCHITECTURE arc1;