music.tan.qmsg

基于FPGA的乐曲发生器设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "4Hz memory lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra0 memory lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] 117.65 MHz 8.5 ns Internal " "Info: Clock \"4Hz\" has Internal fmax of 117.65 MHz between source memory \"lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra0\" and destination memory \"lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]\" (period= 8.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.600 ns + Longest memory memory " "Info: + Longest memory to memory delay is 6.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra0 1 MEM EC4_C 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.600 ns) 6.600 ns lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~mem_cell_ra0 2 MEM EC4_C 1 " "Info: 2: + IC(0.000 ns) + CELL(6.600 ns) = 6.600 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~mem_cell_ra0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 6.600 ns lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] 3 MEM EC4_C 14 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 6.600 ns; Loc. = EC4_C; Fanout = 14; MEM Node = 'lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns ( 100.00 % ) " "Info: Total cell delay = 6.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.600 ns" { lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 6.600ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "4Hz destination 1.900 ns + Shortest memory " "Info: + Shortest clock path from clock \"4Hz\" to destination memory is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns 4Hz 1 CLK PIN_79 44 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 44; CLK Node = '4Hz'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { 4Hz } "NODE_NAME" } } { "music.bdf" "" { Schematic "F:/music/music.bdf" { { 48 -144 24 64 "4Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] 2 MEM EC4_C 14 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = EC4_C; Fanout = 14; MEM Node = 'lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 4Hz {} 4Hz~out {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "4Hz source 1.900 ns - Longest memory " "Info: - Longest clock path from clock \"4Hz\" to source memory is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns 4Hz 1 CLK PIN_79 44 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 44; CLK Node = '4Hz'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { 4Hz } "NODE_NAME" } } { "music.bdf" "" { Schematic "F:/music/music.bdf" { { 48 -144 24 64 "4Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra0 2 MEM EC4_C 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'lrc:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 4Hz {} 4Hz~out {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 4Hz {} 4Hz~out {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 4Hz {} 4Hz~out {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.400 ns + " "Info: + Micro setup delay of destination is 1.400 ns" {  } { { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.600 ns" { lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 6.600ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 4Hz {} 4Hz~out {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 4Hz lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 4Hz {} 4Hz~out {} lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "6MHz yf pulse:inst2\|cq2 15.500 ns register " "Info: tco from clock \"6MHz\" to destination pin \"yf\" through register \"pulse:inst2\|cq2\" is 15.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "6MHz source 5.100 ns + Longest register " "Info: + Longest clock path from clock \"6MHz\" to source register is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns 6MHz 1 CLK PIN_183 13 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 13; CLK Node = '6MHz'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { 6MHz } "NODE_NAME" } } { "music.bdf" "" { Schematic "F:/music/music.bdf" { { -16 -88 80 0 "6MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns pulse:inst2\|cq1 2 REG LC6_G5 1 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC6_G5; Fanout = 1; REG Node = 'pulse:inst2\|cq1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { 6MHz pulse:inst2|cq1 } "NODE_NAME" } } { "pulse.vhd" "" { Text "F:/music/pulse.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 5.100 ns pulse:inst2\|cq2 3 REG LC8_G12 2 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 5.100 ns; Loc. = LC8_G12; Fanout = 2; REG Node = 'pulse:inst2\|cq2'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { pulse:inst2|cq1 pulse:inst2|cq2 } "NODE_NAME" } } { "pulse.vhd" "" { Text "F:/music/pulse.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 31.37 % ) " "Info: Total cell delay = 1.600 ns ( 31.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 68.63 % ) " "Info: Total interconnect delay = 3.500 ns ( 68.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { 6MHz pulse:inst2|cq1 pulse:inst2|cq2 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.100 ns" { 6MHz {} 6MHz~out {} pulse:inst2|cq1 {} pulse:inst2|cq2 {} } { 0.000ns 0.000ns 1.400ns 2.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "pulse.vhd" "" { Text "F:/music/pulse.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.300 ns + Longest register pin " "Info: + Longest register to pin delay is 9.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pulse:inst2\|cq2 1 REG LC8_G12 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_G12; Fanout = 2; REG Node = 'pulse:inst2\|cq2'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { pulse:inst2|cq2 } "NODE_NAME" } } { "pulse.vhd" "" { Text "F:/music/pulse.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(8.600 ns) 9.300 ns yf 2 PIN PIN_121 0 " "Info: 2: + IC(0.700 ns) + CELL(8.600 ns) = 9.300 ns; Loc. = PIN_121; Fanout = 0; PIN Node = 'yf'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { pulse:inst2|cq2 yf } "NODE_NAME" } } { "music.bdf" "" { Schematic "F:/music/music.bdf" { { 48 656 832 64 "yf" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 92.47 % ) " "Info: Total cell delay = 8.600 ns ( 92.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns ( 7.53 % ) " "Info: Total interconnect delay = 0.700 ns ( 7.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { pulse:inst2|cq2 yf } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.300 ns" { pulse:inst2|cq2 {} yf {} } { 0.000ns 0.700ns } { 0.000ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { 6MHz pulse:inst2|cq1 pulse:inst2|cq2 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.100 ns" { 6MHz {} 6MHz~out {} pulse:inst2|cq1 {} pulse:inst2|cq2 {} } { 0.000ns 0.000ns 1.400ns 2.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { pulse:inst2|cq2 yf } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.300 ns" { pulse:inst2|cq2 {} yf {} } { 0.000ns 0.700ns } { 0.000ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 04 22:52:53 2008 " "Info: Processing ended: Thu Dec 04 22:52:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}