music.tan.qmsg

基于FPGA的乐曲发生器设计

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "6MHz " "Info: Assuming node \"6MHz\" is an undefined clock" {  } { { "music.bdf" "" { Schematic "F:/music/music.bdf" { { -16 -88 80 0 "6MHz" "" } } } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "6MHz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "4Hz " "Info: Assuming node \"4Hz\" is an undefined clock" {  } { { "music.bdf" "" { Schematic "F:/music/music.bdf" { { 48 -144 24 64 "4Hz" "" } } } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "4Hz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "pulse:inst2\|cq1 " "Info: Detected ripple clock \"pulse:inst2\|cq1\" as buffer" {  } { { "pulse.vhd" "" { Text "F:/music/pulse.vhd" 12 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "pulse:inst2\|cq1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "6MHz register pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] register pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\] 90.91 MHz 11.0 ns Internal " "Info: Clock \"6MHz\" has Internal fmax of 90.91 MHz between source register \"pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]\" and destination register \"pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\]\" (period= 11.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.200 ns + Longest register register " "Info: + Longest register to register delay is 9.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 1 REG LC8_G4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_G4; Fanout = 3; REG Node = 'pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.500 ns) 2.500 ns pulse:inst2\|Equal0~130 2 COMB LC2_G5 1 " "Info: 2: + IC(1.000 ns) + CELL(1.500 ns) = 2.500 ns; Loc. = LC2_G5; Fanout = 1; COMB Node = 'pulse:inst2\|Equal0~130'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] pulse:inst2|Equal0~130 } "NODE_NAME" } } { "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 4.400 ns pulse:inst2\|Equal0~125 3 COMB LC3_G5 2 " "Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 4.400 ns; Loc. = LC3_G5; Fanout = 2; COMB Node = 'pulse:inst2\|Equal0~125'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { pulse:inst2|Equal0~130 pulse:inst2|Equal0~125 } "NODE_NAME" } } { "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.700 ns) 7.100 ns pulse:inst2\|Equal0~118 4 COMB LC1_G4 12 " "Info: 4: + IC(1.000 ns) + CELL(1.700 ns) = 7.100 ns; Loc. = LC1_G4; Fanout = 12; COMB Node = 'pulse:inst2\|Equal0~118'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { pulse:inst2|Equal0~125 pulse:inst2|Equal0~118 } "NODE_NAME" } } { "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.000 ns) 9.200 ns pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\] 5 REG LC4_G6 4 " "Info: 5: + IC(1.100 ns) + CELL(1.000 ns) = 9.200 ns; Loc. = LC4_G6; Fanout = 4; REG Node = 'pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { pulse:inst2|Equal0~118 pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns ( 66.30 % ) " "Info: Total cell delay = 6.100 ns ( 66.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 33.70 % ) " "Info: Total interconnect delay = 3.100 ns ( 33.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.200 ns" { pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] pulse:inst2|Equal0~130 pulse:inst2|Equal0~125 pulse:inst2|Equal0~118 pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.200 ns" { pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] {} pulse:inst2|Equal0~130 {} pulse:inst2|Equal0~125 {} pulse:inst2|Equal0~118 {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] {} } { 0.000ns 1.000ns 0.000ns 1.000ns 1.100ns } { 0.000ns 1.500ns 1.900ns 1.700ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "6MHz destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"6MHz\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns 6MHz 1 CLK PIN_183 13 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 13; CLK Node = '6MHz'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { 6MHz } "NODE_NAME" } } { "music.bdf" "" { Schematic "F:/music/music.bdf" { { -16 -88 80 0 "6MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\] 2 REG LC4_G6 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_G6; Fanout = 4; REG Node = 'pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[10\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 6MHz {} 6MHz~out {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "6MHz source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"6MHz\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns 6MHz 1 CLK PIN_183 13 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 13; CLK Node = '6MHz'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { 6MHz } "NODE_NAME" } } { "music.bdf" "" { Schematic "F:/music/music.bdf" { { -16 -88 80 0 "6MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC8_G4 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_G4; Fanout = 3; REG Node = 'pulse:inst2\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 6MHz {} 6MHz~out {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 6MHz {} 6MHz~out {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 6MHz {} 6MHz~out {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.200 ns" { pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] pulse:inst2|Equal0~130 pulse:inst2|Equal0~125 pulse:inst2|Equal0~118 pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.200 ns" { pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] {} pulse:inst2|Equal0~130 {} pulse:inst2|Equal0~125 {} pulse:inst2|Equal0~118 {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] {} } { 0.000ns 1.000ns 0.000ns 1.000ns 1.100ns } { 0.000ns 1.500ns 1.900ns 1.700ns 1.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 6MHz {} 6MHz~out {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { 6MHz pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { 6MHz {} 6MHz~out {} pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}