music.hier_info

基于FPGA的乐曲发生器设计

|music
yf <= pulse:inst2.fout
6MHz => pulse:inst2.clk
4Hz => lrc:inst3.inclock
4Hz => lrc:inst3.outclock
4Hz => find:inst.clk
en => find:inst.EN


|music|pulse:inst2
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => cq1.CLK
d[0] => count~13.DATAB
d[1] => count~12.DATAB
d[2] => count~11.DATAB
d[3] => count~10.DATAB
d[4] => count~9.DATAB
d[5] => count~8.DATAB
d[6] => count~7.DATAB
d[7] => count~6.DATAB
d[8] => count~5.DATAB
d[9] => count~4.DATAB
d[10] => count~3.DATAB
d[11] => count~2.DATAB
d[12] => count~1.DATAB
d[13] => count~0.DATAB
fout <= cq2.DB_MAX_OUTPUT_PORT_TYPE


|music|change:inst1
DIN[0] => Mux14.IN134
DIN[0] => Mux13.IN134
DIN[0] => Mux12.IN134
DIN[0] => Mux11.IN134
DIN[0] => Mux10.IN134
DIN[0] => Mux9.IN134
DIN[0] => Mux8.IN134
DIN[0] => Mux7.IN134
DIN[0] => Mux6.IN134
DIN[0] => Mux5.IN134
DIN[0] => Mux4.IN134
DIN[0] => Mux3.IN134
DIN[0] => Mux2.IN134
DIN[0] => Mux1.IN134
DIN[0] => Mux0.IN134
DIN[1] => Mux14.IN133
DIN[1] => Mux13.IN133
DIN[1] => Mux12.IN133
DIN[1] => Mux11.IN133
DIN[1] => Mux10.IN133
DIN[1] => Mux9.IN133
DIN[1] => Mux8.IN133
DIN[1] => Mux7.IN133
DIN[1] => Mux6.IN133
DIN[1] => Mux5.IN133
DIN[1] => Mux4.IN133
DIN[1] => Mux3.IN133
DIN[1] => Mux2.IN133
DIN[1] => Mux1.IN133
DIN[1] => Mux0.IN133
DIN[2] => Mux14.IN132
DIN[2] => Mux13.IN132
DIN[2] => Mux12.IN132
DIN[2] => Mux11.IN132
DIN[2] => Mux10.IN132
DIN[2] => Mux9.IN132
DIN[2] => Mux8.IN132
DIN[2] => Mux7.IN132
DIN[2] => Mux6.IN132
DIN[2] => Mux5.IN132
DIN[2] => Mux4.IN132
DIN[2] => Mux3.IN132
DIN[2] => Mux2.IN132
DIN[2] => Mux1.IN132
DIN[2] => Mux0.IN132
DIN[3] => Mux14.IN131
DIN[3] => Mux13.IN131
DIN[3] => Mux12.IN131
DIN[3] => Mux11.IN131
DIN[3] => Mux10.IN131
DIN[3] => Mux9.IN131
DIN[3] => Mux8.IN131
DIN[3] => Mux7.IN131
DIN[3] => Mux6.IN131
DIN[3] => Mux5.IN131
DIN[3] => Mux4.IN131
DIN[3] => Mux3.IN131
DIN[3] => Mux2.IN131
DIN[3] => Mux1.IN131
DIN[3] => Mux0.IN131
af[0] <= af[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[1] <= af[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[2] <= af[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[3] <= af[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[4] <= af[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[5] <= af[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[6] <= af[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[7] <= af[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[8] <= af[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[9] <= af[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[10] <= af[10]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[11] <= af[11]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[12] <= af[12]$latch.DB_MAX_OUTPUT_PORT_TYPE
af[13] <= af[13]$latch.DB_MAX_OUTPUT_PORT_TYPE


|music|lrc:inst3
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
address[7] => lpm_rom:lpm_rom_component.address[7]
inclock => lpm_rom:lpm_rom_component.inclock
outclock => lpm_rom:lpm_rom_component.outclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]


|music|lrc:inst3|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => altrom:srom.clocki
outclock => altrom:srom.clocko
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE


|music|lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => segment[0][3].CLK1
clocko => segment[0][2].CLK1
clocko => segment[0][1].CLK1
clocko => segment[0][0].CLK1
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT


|music|find:inst
clk => counter[7].CLK
clk => counter[6].CLK
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
EN => process0~0.IN1
add[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
add[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
add[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
add[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
add[4] <= counter[4].DB_MAX_OUTPUT_PORT_TYPE
add[5] <= counter[5].DB_MAX_OUTPUT_PORT_TYPE
add[6] <= counter[6].DB_MAX_OUTPUT_PORT_TYPE
add[7] <= counter[7].DB_MAX_OUTPUT_PORT_TYPE