change.vhd.bak

基于FPGA的乐曲发生器设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY change IS
PORT(DIN:IN STD_LOGIC_vector(3 DOWNTO 0);
      af:OUT INTEGER RANGE 0 TO 16#3FFF#);
END;
ARCHITECTURE one OF change IS
CONSTANT low_1:INTEGER:=11467;
CONSTANT low_2:INTEGER:=10216;
CONSTANT low_3:INTEGER:=9101;
CONSTANT low_4:INTEGER:=8590;
CONSTANT low_5:INTEGER:=7653;
CONSTANT LOW_6: INTEGER:=6817;
CONSTANT LOW_7: INTEGER:=6073;
CONSTANT MID_1: INTEGER:=5732;
CONSTANT MID_2: INTEGER:=5107;
CONSTANT MID_3: INTEGER:=4550; 
CONSTANT MID_4: INTEGER:=4295; 
CONSTANT MID_5: INTEGER:=3826;
CONSTANT MID_6: INTEGER:=3408;
CONSTANT MID_7: INTEGER:=3037;
CONSTANT HIGH_1:INTEGER:=2866;
CONSTANT HIGH_2:INTEGER:=2554;
CONSTANT HIGH_3:INTEGER:=2275;
CONSTANT HIGH_4:INTEGER:=2148;
CONSTANT HIGH_5:INTEGER:=1913;
CONSTANT HIGH_6:INTEGER:=1706;
CONSTANT HIGH_7:INTEGER:=1519;
CONSTANT stop:  INTEGER:=0;
SIGNAL counter:INTEGER RANGE 0 TO 138;
BEGIN
   PROCESS(counter)
         BEGIN
         counter<=CONV_INTEGER(DIN);
           CASE counter IS
WHEN    0   =>af<=stop;
WHEN    1   =>af<=low_1;
WHEN    2   =>af<=low_2;
WHEN	3	=>af<=low_3;
WHEN    4   =>af<=low_4;
WHEN	5	=>af<=low_5;
WHEN	6	=>af<=low_6;
WHEN	7	=>af<=low_7;
WHEN	8	=>af<=mid_1;
WHEN	9	=>af<=mid_2;
WHEN	10	=>af<=mid_3;
WHEN	11	=>af<=mid_4;
WHEN	12	=>af<=mid_5;
WHEN	13	=>af<=mid_6;
WHEN	14	=>af<=mid_7;
WHEN	15	=>af<=high_1;
WHEN	16	=>af<=high_2;
WHEN	17	=>af<=high_3;
WHEN	18	=>af<=high_4;
WHEN	19	=>af<=high_5;
WHEN	20	=>af<=high_6;
WHEN	21	=>af<=high_7;
WHEN OTHERS=>NULL;
         END CASE;
    END PROCESS;
END;