find.vhd.bak

基于FPGA的乐曲发生器设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY find IS
PORT(clk,EN:IN STD_LOGIC;
     add:out STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE one OF find IS
SIGNAL counter:INTEGER RANGE 0 TO 138;
BEGIN
   PROCESS(clk,EN)
       BEGIN
       IF counter=138 OR EN='0' THEN counter<=0;
       ELSIF (clk'EVENT AND clk='1')THEN
       counter<=counter+1;
       END IF; 
  add<=CONV_STD_LOGIC_VECTOR(counter,8);  
  END PROCESS;
END;