music.map.rpt

基于FPGA的乐曲发生器设计

+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: find:inst|lpm_counter:counter_rtl_1 ;
+------------------------+-------------------+-----------------------------------------+
; Parameter Name         ; Value             ; Type                                    ;
+------------------------+-------------------+-----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                          ;
; LPM_WIDTH              ; 8                 ; Untyped                                 ;
; LPM_DIRECTION          ; UP                ; Untyped                                 ;
; LPM_MODULUS            ; 0                 ; Untyped                                 ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                 ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                 ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                 ;
; DEVICE_FAMILY          ; ACEX1K            ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                      ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                      ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                 ;
; LABWIDE_SCLR           ; ON                ; Untyped                                 ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                 ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                 ;
+------------------------+-------------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Dec 04 22:52:33 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off music -c music
Info: Found 1 design units, including 1 entities, in source file music.bdf
    Info: Found entity 1: music
Info: Elaborating entity "music" for the top level hierarchy
Warning: Using design file pulse.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pulse-behav
    Info: Found entity 1: pulse
Info: Elaborating entity "pulse" for hierarchy "pulse:inst2"
Warning (10492): VHDL Process Statement warning at pulse.vhd(26): signal "cq" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at pulse.vhd(39): signal "cq2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file change.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: change-one
    Info: Found entity 1: change
Info: Elaborating entity "change" for hierarchy "change:inst1"
Warning (10492): VHDL Process Statement warning at change.vhd(36): signal "DIN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at change.vhd(34): inferring latch(es) for signal or variable "af", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "af[0]" at change.vhd(34)
Info (10041): Inferred latch for "af[1]" at change.vhd(34)
Info (10041): Inferred latch for "af[2]" at change.vhd(34)
Info (10041): Inferred latch for "af[3]" at change.vhd(34)
Info (10041): Inferred latch for "af[4]" at change.vhd(34)
Info (10041): Inferred latch for "af[5]" at change.vhd(34)
Info (10041): Inferred latch for "af[6]" at change.vhd(34)
Info (10041): Inferred latch for "af[7]" at change.vhd(34)
Info (10041): Inferred latch for "af[8]" at change.vhd(34)
Info (10041): Inferred latch for "af[9]" at change.vhd(34)
Info (10041): Inferred latch for "af[10]" at change.vhd(34)
Info (10041): Inferred latch for "af[11]" at change.vhd(34)
Info (10041): Inferred latch for "af[12]" at change.vhd(34)
Info (10041): Inferred latch for "af[13]" at change.vhd(34)
Warning: Using design file lrc.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lrc-SYN
    Info: Found entity 1: lrc
Info: Elaborating entity "lrc" for hierarchy "lrc:inst3"
Info: Found 1 design units, including 1 entities, in source file e:/quartus/libraries/megafunctions/lpm_rom.tdf
    Info: Found entity 1: lpm_rom
Info: Elaborating entity "lpm_rom" for hierarchy "lrc:inst3|lpm_rom:lpm_rom_component"
Info: Elaborated megafunction instantiation "lrc:inst3|lpm_rom:lpm_rom_component"
Info: Found 1 design units, including 1 entities, in source file e:/quartus/libraries/megafunctions/altrom.tdf
    Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom"
Info: Elaborated megafunction instantiation "lrc:inst3|lpm_rom:lpm_rom_component|altrom:srom", which is child of megafunction instantiation "lrc:inst3|lpm_rom:lpm_rom_component"
Info: Instantiated megafunction "lrc:inst3|lpm_rom:lpm_rom_component" with the following parameter:
    Info: Parameter "intended_device_family" = "ACEX1K"
    Info: Parameter "lpm_address_control" = "REGISTERED"
    Info: Parameter "lpm_file" = "music.hex"
    Info: Parameter "lpm_outdata" = "REGISTERED"
    Info: Parameter "lpm_type" = "LPM_ROM"
    Info: Parameter "lpm_width" = "4"
    Info: Parameter "lpm_widthad" = "8"
Warning: Using design file find.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: find-one
    Info: Found entity 1: find
Info: Elaborating entity "find" for hierarchy "find:inst"
Warning (10492): VHDL Process Statement warning at find.vhd(14): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at find.vhd(18): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: LATCH primitive "change:inst1|af[1]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[0]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[2]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[3]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[4]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[5]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[6]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[7]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[8]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[9]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[10]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[11]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[12]" is permanently enabled
Warning: LATCH primitive "change:inst1|af[13]" is permanently enabled
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=14) from the following logic: "pulse:inst2|count[0]~14"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "find:inst|counter[0]~0"
Info: Found 1 design units, including 1 entities, in source file e:/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "pulse:inst2|lpm_counter:count_rtl_0"
Info: Found 1 design units, including 1 entities, in source file e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "pulse:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "pulse:inst2|lpm_counter:count_rtl_0"
Info: Instantiated megafunction "pulse:inst2|lpm_counter:count_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "14"
    Info: Parameter "LPM_DIRECTION" = "DOWN"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "find:inst|lpm_counter:counter_rtl_1"
Info: Elaborated megafunction instantiation "find:inst|lpm_counter:counter_rtl_1|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "find:inst|lpm_counter:counter_rtl_1"
Info: Instantiated megafunction "find:inst|lpm_counter:counter_rtl_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Warning: Converting TRI node "lrc:inst3|lpm_rom:lpm_rom_component|otri[0]" that feeds logic to an OR gate
Warning: Converting TRI node "lrc:inst3|lpm_rom:lpm_rom_component|otri[1]" that feeds logic to an OR gate
Warning: Converting TRI node "lrc:inst3|lpm_rom:lpm_rom_component|otri[2]" that feeds logic to an OR gate
Warning: Converting TRI node "lrc:inst3|lpm_rom:lpm_rom_component|otri[3]" that feeds logic to an OR gate
Info: Implemented 53 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 45 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings
    Info: Allocated 156 megabytes of memory during processing
    Info: Processing ended: Thu Dec 04 22:52:37 2008
    Info: Elapsed time: 00:00:04