📄 alu算术逻辑运算模块设计.txt
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ALU算术逻辑运算模块设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY alu IS
PORT( R,S : IN UNSIGNED(3 DOWNTO 0);
ALU_CTRL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
CIN: IN STD_LOGIC;
F:BUFFER UNSIGNED(3 DOWNTO 0);
G_BAR,P_BAR: BUFFER STD_LOGIC;
C4:BUFFER STD_LOGIC;
OVR:BUFFER STD_LOGIC );
END ENTITY alu ;
ARCHITECTURE arc1 OF alu IS
SIGNAL R1,S1,F1:UNSIGNED(4 DOWNTO 0);
BEGIN
R1<= '0'&R;
S1<= '0'&S;
PROCESS(R1,S1,CIN,ALU_CTRL)
BEGIN
CASE ALU_CTRL IS
WHEN "000" =>
IF CIN='0' THEN
F1<= R1 + S1;
ELSE
F1<= R1 + S1 + 1;
END IF;
WHEN "001" =>
IF CIN='0' THEN
F1<= S1 + NOT(R1);
ELSE
F1<= S1 + NOT(R1)+1;
END IF;
WHEN "010" =>
IF CIN='0' THEN
F1<= R1 + NOT(S1);
ELSE
F1<= R1 + NOT(S1)+1;
END IF;
WHEN "011" => F1<=R1 OR S1;
WHEN "100" => F1<=R1 AND S1;
WHEN "101" => F1<= (NOT R1) AND S1;
WHEN "110" => F1<=R1 XOR S1;
WHEN "111" => F1<=NOT(R1 XOR S1);
WHEN OTHERS=> F1<="--";
END CASE;
END PROCESS;
F<=F1(3 DOWNTO 0);
C4<= F1(4);
G_BAR<= NOT(
(R(3) AND S(3)) OR
((R(3) OR S(3)) AND (R(2) AND S(2))) OR
((R(3) OR S(3)) AND (R(2) OR S(2)) AND (R(1) AND S(1))) OR
((R(3) OR S(3)) AND (R(2) OR S(2)) AND (R(1) AND S(1)) AND
(R(0) AND S(0))) );
P_BAR<= NOT (
(R(3) OR S(3)) AND (R(2) OR S(2)) AND (R(1) AND S(1)) AND
(R(0) AND S(0)) );
OVR <= '1' WHEN (F1(4)/=F1(3)) ELSE '0';
END ARCHITECTURE arc1;
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