加法器示例程序.txt

来自「加法器和全加器参考程序」· 文本 代码 · 共 28 行

加法器示例程序。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY sadder IS
   PORT(
      a,b,c,d:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      s:IN STD_LOGIC;  
      q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      cout:OUT STD_LOGIC);

END ENTITY sadder;

ARCHITECTURE arc1 OF sadder IS
SIGNAL tmp: STD_LOGIC_VECTOR(4 DOWNTO 0);
 BEGIN
     PROCESS(a,b,c,d,s)
       BEGIN
           IF s='0' THEN tmp<=('0'&a)+('0'&b);
              ELSE tmp<=('0'&c)+('0'&d);
           END IF;
     END PROCESS;
     q<= tmp(3)&tmp(2)&tmp(1)&tmp(0);
      cout<=tmp(4);
 END ARCHITECTURE arc1;