scc.vhd

Usart model in vhdl code

-- ------------------------------------------------------------------------- --
-- ------------------------------------------------------------------------- --
--                                                                           --
-- File................: SCC.VHD                                             --
-- Function............: SCC controller (non-dedicated)                      --
-- Components Required.: Clock_gen.vhd, Tx_sync, Tx_async, Rx_sync, Rx_async --
-- Compilation Notes...: None.                                               --
--                                                                           --
-- Revision History:                                                         --
--   1.00 Initial intent release                                             --
--                                                                           --
-- ------------------------------------------------------------------------- --
--                                                                           --
-- Revision History:                                                         --
--                    
--
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SCC is port (
    reset_n         : in        std_logic;
    clk             : in        std_logic;
    WR_rx           : in        std_logic;
    read_rx         : in        std_logic;
    SCC_data_in     : in        std_logic_vector(7 downto 0);
    SCCrx           : in        std_logic;
    baud_val       : in        std_logic_vector(15 downto 0);
    -- Configuration bits
    bit8            : in        std_logic; -- if set to one 8 data bits otherwise 7 data bits
    parity_en       : in        std_logic; -- if set to one parity is enabled otherwise disabled
    odd_n_even      : in        std_logic; -- if set to one odd parity otherwise even parity
    
    -- Status bits
    parity_err      : out       std_logic; -- parity error indicator on recieved data
    overflow        : out       std_logic; -- receiver overflow
    txrdy           : out       std_logic; -- transmit ready for another byte
    receive_full    : out       std_logic; -- receiver has a byte ready
    SCC_data_out    : out       std_logic_vector(7 downto 0);
    SCCtx           : out       std_logic
);
end SCC;

architecture rtl of SCC is

-----------------------------------------------------------
-- COMPONENT DECLARATIONS
-----------------------------------------------------------

    component Tx_async port (
       clk                    : in  std_logic;                     -- system clock
       xmit_pulse             : in  std_logic;                     -- transmit pulse
       reset_n                : in  std_logic;                     -- active low async reset
       rst_tx_empty           : in  std_logic;                     -- reset transmit empty
       tx_hold_reg            : in  std_logic_vector(7 downto 0);  -- transmit byte hold register
       bit8                   : in  std_logic;                     -- if set to one 8 data bits otherwise 7 data bits
       parity_en              : in  std_logic;                     -- if set to one parity is enabled otherwise disabled
       odd_n_even             : in  std_logic;                     -- if set to one odd parity otherwise even parity
       txrdy                  : out std_logic;                     -- transmit ready for another byte
       SCCtx                  : out std_logic                      -- serial data stream out
      );
   end component;

   component Rx_async port (
       clk                   : in   std_logic;                     -- system clock
       baud_clock            : in   std_logic;                     -- 8x baud clock pulse
       reset_n               : in   std_logic;                     -- active low async reset  
       bit8                  : in   std_logic;                     -- if set to one 8 data bits otherwise 7 data bits
       parity_en             : in   std_logic;                     -- if set to one parity is enabled otherwise disabled
       odd_n_even            : in   std_logic;                     -- if set to one odd parity otherwise even parity
       read_rx_byte          : in   std_logic;                     -- read rx byte register
       SCCrx                 : in   std_logic;

       overflow              : out  std_logic;                     -- receiver overflow
       parity_err            : out  std_logic;                     -- parity error indicator on recieved data
       receive_full          : out  std_logic;                     -- receiver has a byte ready
       rx_byte               : out  std_logic_vector(7 downto 0)   -- receive byte register
      );
   end component;


   component Clock_gen port (
             clk              : in   std_logic;                     -- system clock
             reset_n          : in   std_logic;                     -- active low async reset  
             baud_val        : in   std_logic_vector(15 downto 0);  -- value loaded into cntr 

             baud_clock       : out  std_logic;                     -- 8x baud clock pulse
             xmit_pulse       : out  std_logic                      -- transmit pulse
            );
   end component;

--------------------------------------------------------
-- INTERNAL SIGNAL DECLARATIONS
--------------------------------------------------------

    signal xmit_pulse       : std_logic;                     -- transmit pulse
    signal baud_clock       : std_logic;                     -- 8x baud clock pulse
    signal rst_tx_empty     : std_logic;                     -- reset transmit empty
    signal tx_hold_reg      : std_logic_vector(7 downto 0);  -- transmit byte hold register
    signal read_rx_byte     : std_logic;                     -- read rx byte register
    signal rx_byte          : std_logic_vector(7 downto 0);  -- receive byte register

--------------------------------------------------------
-- MODE CONSTANT, 1 for synchronous 0 for asynchronous
--------------------------------------------------------
    constant SYNCHRONOUS  : std_logic := '0';

begin

------------------------------------------------------------------------------
-- cpu writes to SCC registers
------------------------------------------------------------------------------
reg_write : process(clk, reset_n)
begin    
if(reset_n = '0') then
    tx_hold_reg <= (others => '0');  
elsif(clk'event and clk = '1') then
    if(wr_rx='1') then
      tx_hold_reg <= SCC_data_in;
    end if;      
end if;
end process;

rst_tx_empty <= wr_rx;

------------------------------------------------------------------------------
-- cpu reads from SCC registers
------------------------------------------------------------------------------
--SCC_data_out <= rx_byte when OEn = '0' and SCC_csn = '0' else (others => '0');
SCC_data_out <= rx_byte;


read_rx_byte <= read_rx;

make_CLOCK_GEN : 
     Clock_gen port map (
                         clk        => clk,
                         reset_n    => reset_n,
                         baud_val  => baud_val,
                         baud_clock => baud_clock,
                         xmit_pulse => xmit_pulse
                        );

make_TX :
     Tx_async port map (
                        clk          => clk,
                        xmit_pulse   => xmit_pulse,
                        reset_n      => reset_n,
                        rst_tx_empty => rst_tx_empty,
                        tx_hold_reg  => tx_hold_reg,
                        bit8         => bit8,
                        parity_en    => parity_en,
                        odd_n_even   => odd_n_even,
                        txrdy        => txrdy,
                        SCCtx        => SCCtx
                       );

make_RX : 
     Rx_async port map (
                        clk          => clk,
                        baud_clock   => baud_clock,
                        reset_n      => reset_n,
                        bit8         => bit8,
                        parity_en    => parity_en,
                        odd_n_even   => odd_n_even,
                        read_rx_byte => read_rx_byte,
                        SCCrx        => SCCrx,
                        overflow     => overflow,
                        parity_err   => parity_err,
                        receive_full => receive_full,
                        rx_byte      => rx_byte
                       );

END rtl;