tx_async.vhd

Usart model in vhdl code

-- File................: TX_ASYNC.VHD
-- Function............: Perform the asynchronous transmit function for the SCC
-- Component of........: SCC.VHD
-- Components Required.: NONE
-- Compilation Notes...:
--

-- Functional Description:
--

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

entity Tx_async is port (
       clk                : in  std_logic;                     -- system clock
       xmit_pulse         : in  std_logic;                     -- transmit pulse
       reset_n            : in  std_logic;                     -- active low async reset
       rst_tx_empty       : in  std_logic;                     -- reset transmit empty
       tx_hold_reg        : in  std_logic_vector(7 downto 0);  -- transmit byte hold register
       bit8               : in  std_logic;                     -- if set to one 8 data bits otherwise 7 data bits
       parity_en          : in  std_logic;                     -- if set to one parity is enabled otherwise disabled
       odd_n_even         : in  std_logic;                     -- if set to one odd parity otherwise even parity

       txrdy              : out std_logic;                     -- transmit ready for another byte
       SCCtx              : out std_logic                      -- serial data stream out
);
end Tx_async;

architecture rtl of Tx_async is

type transmit_states is (tx_idle, tx_load, start_bit, tx_data_bits, parity_bit, tx_stop_bit);


signal xmit_state       : transmit_states;               -- transmit state machine
signal txrdy_int        : std_logic;                     -- transmit ready for another byte
signal tx_byte          : std_logic_vector(7 downto 0);  -- transmit byte
signal xmit_bit_sel     : std_logic_vector(3 downto 0);  -- selects transmit bit
signal tx_parity        : std_logic;                     -- transmit parity
signal set_rdy        : std_logic;                     -- aggiunto da gpt

begin

------------------------------------------------------------------------------
make_txrdy:  --  make the transmitter ready signal
------------------------------------------------------------------------------
process(clk, reset_n)
begin
if (reset_n = '0') then
    txrdy_int <= '1';
elsif (clk'event and clk = '1') then
--  if(xmit_pulse = '1') then
---- set transmit empty after transition from stop_bit state to idle state    
--    if (xmit_state = tx_load) then
--        txrdy_int <= '1';
--    end if;      
--  end if;
  if(set_rdy = '1') then
    txrdy_int <= '1';
  end if;

  if(rst_tx_empty = '1') then
    txrdy_int <= '0';
  end if;
end if;    
end process;

------------------------------------------------------------------------------
xmit_sm  :  -- transmit state machine
------------------------------------------------------------------------------
process (clk, reset_n)
begin
if (reset_n = '0') then
    xmit_state  <= tx_idle;
    tx_byte     <= (others => '0');
elsif (clk'event and clk = '1') then
  if(xmit_pulse = '1') then
        case xmit_state is
            when tx_idle       => if(txrdy_int = '0') then
                                    xmit_state <= tx_load;
                                  else
                                    xmit_state <= tx_idle;
                                  end if;
            when tx_load       => tx_byte <= tx_hold_reg;
                                  xmit_state <= start_bit;
            when start_bit     => xmit_state <= tx_data_bits;

            when tx_data_bits  => if(BIT8='1') then
                                    if (xmit_bit_sel = "0111") then
                                      if(parity_en = '1') then
                                        xmit_state <= parity_bit;
                                      else
                                        xmit_state <= tx_stop_bit;
                                      end if;
                                    else
                                      xmit_state <= tx_data_bits;
                                    end if;
                                  else
                                    if (xmit_bit_sel = "0110") then
                                     if(parity_en = '1') then
                                       xmit_state <= parity_bit;
                                     else
                                       xmit_state <= tx_stop_bit;
                                     end if;
                                    else
                                      xmit_state <= tx_data_bits;
                                    end if;
                                  end if;
                                   
            when parity_bit    => xmit_state <= tx_stop_bit;

            when tx_stop_bit   => xmit_state <= tx_idle;
            
            when others        => xmit_state <= tx_idle;
        end case;
  end if;
end if;
end process;

------------------------------------------------------------------------------
xmit_cnt  :  -- transmit bits counter
------------------------------------------------------------------------------
process (clk, reset_n)
begin
if (reset_n = '0') then
    xmit_bit_sel <= "0000";
elsif (clk'event and clk = '1') then
  if(xmit_pulse = '1') then
    if (xmit_state /= tx_data_bits) then
        xmit_bit_sel <= "0000";
    else
        xmit_bit_sel <= xmit_bit_sel + '1';
    end if;
  end if;
end if;
end process;

------------------------------------------------------------------------------
xmit_sel  :  -- transmit data mux
------------------------------------------------------------------------------
process (clk, reset_n)
begin
if (reset_n = '0') then
    SCCtx <= '1';
set_rdy<='0';
elsif (clk'event and clk = '1') then
set_rdy<='0';
  if(xmit_pulse = '1') then
    case xmit_state is
        when tx_idle       => SCCtx <= '1';
        when tx_load       => SCCtx <= '1';
        when start_bit     => SCCtx <= '0';
        when tx_data_bits  => SCCtx <= tx_byte(conv_integer(xmit_bit_sel(2 Downto 0)));
        when parity_bit    => SCCtx <= ODD_N_EVEN xor tx_parity;
        --when parity_bit    => if(ODD_N_EVEN = '1') then
        --                        SCCtx <= not tx_parity;
        --                      else
        --                        SCCtx <= tx_parity;
        --                      end if;
        when tx_stop_bit   => SCCtx <= '1';
		  								set_rdy<='1';
        when others        => SCCtx <= '1';
		  								set_rdy<='0';
    end case;
  end if;
end if;
end process;

------------------------------------------------------------------------------
xmit_par_calc : -- transmit even or odd parity calculation
------------------------------------------------------------------------------
process (clk, reset_n)
begin
if (reset_n = '0') then
   tx_parity <= '0';
elsif (clk'event and clk = '1') then
  if(xmit_pulse = '1' and PARITY_EN = '1') then
    if (xmit_state = tx_data_bits) then
      tx_parity <= tx_parity xor tx_byte(conv_integer(xmit_bit_sel(2 Downto 0)));
    else 
      tx_parity <= tx_parity;
    end if;
  end if;
  if(xmit_state = tx_stop_bit) then
    tx_parity <= '0';
  end if;
end if;
end process;


txrdy <= txrdy_int;

end rtl;