mediamobile.vhd

moving average vhdl source code

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-----------------------------------------------------------------------------
-- Entity: 	MediaMobile
-- File:	MediaMobile.vhd
-- Description:	Dummy version of MediaMobile 
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all; 
use IEEE.Std_Logic_arith.all; 
use IEEE.Std_Logic_unsigned.all;

entity MediaMobile is port(
Mclock      :in std_logic;                                   -- Master Clock
Reset      :in std_logic;                                   -- Reset
A           :in std_logic_vector(7 downto 0);                -- Ingresso
Y           :OUT std_logic_vector(7 downto 0)                -- 
 );
end;

architecture rtl of MediaMobile is
--------------------------------------------------------------------------------
Constant Nbit : integer range 0 to 7 :=5;
Constant Profondita : integer range 1 to 256 :=2^Nbit;

type Lut_memtype is array (Profondita-1 downto 0) of std_logic_vector(7 downto 0);
signal mem : Lut_memtype;
Signal Somma : std_logic_vector(Nbit + 7 downto 0);
Constant AllZero : std_logic_vector(Nbit-1 downto 0):=(others=>'0');
begin



Process(Mclock)
begin
if Mclock'event and Mclock='1' then
	mem(0) <= A;
	Mem(Profondita-1 downto 1)<= Mem(Profondita-2 downto 0);
end if;
end process;



Process(Mclock,reset)
begin
if reset='0' then 
Somma <=(others=>'0');
elsif Mclock'event and Mclock='1' then
	Somma <= Somma + (AllZero & A) - (AllZero & Mem(Profondita-1)) ;
end if;
end process;
Y<=Somma(Nbit + 7 downto Nbit);



end;