my_encode.srr

verilog 编码程序

#Build: Synplify 9.6A, Build 069R, Nov  3 2008
#install: D:\Actel\Libero_v8.5\Synplify\synplify_96A
#OS: Windows XP 5.1
#Hostname: GENGTIANXIANG

#Implementation: synthesis

#Mon Mar 09 15:47:03 2009

$ Start of Compile
#Mon Mar 09 15:47:03 2009

Synplicity Verilog Compiler, version 1.0, Build 157R, built Nov  5 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"D:\Actel\Libero_v8.5\Synplify\synplify_96A\lib\proasic\proasic3.v"
@I::"E:\work\EasyFPGA030\my_encode\hdl\my_encode.v"
@E: CG105 :"E:\work\EasyFPGA030\my_encode\hdl\my_encode.v":25:7:25:7|range on instances are legal in Vlog-2001 mode
@E: CS187 :"E:\work\EasyFPGA030\my_encode\hdl\my_encode.v":41:0:41:8|Expecting endmodule
2 syntax errors
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Mar 09 15:47:03 2009

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