busdelay.vhd

buffer delay vhdl model

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-- Entity: 	AntiRimbalzo
-- File:	BusDelay.vhd
-- Description:	Dummy version of BusDelay 
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library IEEE;
use IEEE.Std_Logic_1164.all; 
use IEEE.Std_Logic_arith.all; 
use IEEE.Std_Logic_unsigned.all;

entity BusDelay is port(
Mclock      :in std_logic;                                   -- Master Clock
A           :in std_logic_vector(7 downto 0);                -- Ingresso
Y           :OUT std_logic_vector(7 downto 0)                -- Uscita Ritardata di 16 Mclock
 );
end;

architecture rtl of BusDelay is
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type Lut_memtype is array (15 downto 0) of std_logic_vector(7 downto 0);
signal mem : Lut_memtype;

begin

Process(Mclock)
begin
if Mclock'event and Mclock='1' then
	mem(0) <= A;
	Mem(15 downto 1)<= Mem(14 downto 0);
end if;
end process;
Y<Mem(15);

end;