bjqcondff.map.qmsg

很多仪器都输出同步时钟

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ce bjq.vhd(21) " "Warning: VHDL Process Statement warning at bjq.vhd(21): signal \"ce\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "rd bjq.vhd(23) " "Warning: VHDL Process Statement warning at bjq.vhd(23): signal \"rd\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s bjq.vhd(61) " "Warning: VHDL Process Statement warning at bjq.vhd(61): signal \"s\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dfftodsp0 bjq.vhd(62) " "Warning: VHDL Process Statement warning at bjq.vhd(62): signal \"dfftodsp0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dfftodsp1 bjq.vhd(63) " "Warning: VHDL Process Statement warning at bjq.vhd(63): signal \"dfftodsp1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dfftodsp2 bjq.vhd(64) " "Warning: VHDL Process Statement warning at bjq.vhd(64): signal \"dfftodsp2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 64 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dfftodsp3 bjq.vhd(65) " "Warning: VHDL Process Statement warning at bjq.vhd(65): signal \"dfftodsp3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dfftodsp4 bjq.vhd(66) " "Warning: VHDL Process Statement warning at bjq.vhd(66): signal \"dfftodsp4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ren0 bjq.vhd(19) " "Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable \"ren0\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ren0\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ren1 bjq.vhd(19) " "Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable \"ren1\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ren1\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ren2 bjq.vhd(19) " "Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable \"ren2\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ren2\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ren3 bjq.vhd(19) " "Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable \"ren3\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ren3\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ren4 bjq.vhd(19) " "Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable \"ren4\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ren4\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ren5 bjq.vhd(19) " "Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable \"ren5\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ren5\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ed bjq.vhd(19) " "Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable \"ed\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ed\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bjq.vhd" "" { Text "C:/Documents and Settings/Tommyang/桌面/gytask/interface/bjq.vhd" 19 0 0 } }  } 0}