bjqcondff.tan.rpt

来自「很多仪器都输出同步时钟」· RPT 代码 · 共 180 行 · 第 1/5 页

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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                                                                                                              ; To                                                                                                     ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 5.570 ns                         ; dspwe                                                                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[51]                                                  ;                              ; clk                          ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                                                          ; altera_reserved_tdo                                                                                    ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.844 ns                         ; altera_internal_jtag                                                                                                                                                                                                                                              ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]                                             ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 118.88 MHz ( period = 8.412 ns ) ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                                                                                                           ; sld_hub:sld_hub_inst|hub_tdo                                                                           ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 129.23 MHz ( period = 7.738 ns ) ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|match_out ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] ; clk                          ; clk                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                                                                                                                   ;                                                                                                        ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;