test.map.rpt

很多仪器都输出同步时钟

; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; test.vhd                         ; yes             ; User VHDL File  ; E:/gytask/test11/test.vhd    ;
+----------------------------------+-----------------+-----------------+------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 0         ;
; Total combinational functions   ; 0         ;
;     -- Total 4-input functions  ; 0         ;
;     -- Total 3-input functions  ; 0         ;
;     -- Total 2-input functions  ; 0         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 0         ;
; I/O pins                        ; 17        ;
+---------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |test                      ; 0 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 17   ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |test               ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/gytask/test11/test.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Jun 06 11:20:21 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Info: Found 2 design units, including 1 entities, in source file test.vhd
    Info: Found design unit 1: test-bhv
    Info: Found entity 1: test
Info: Elaborating entity "test" for the top level hierarchy
Info: Power-up level of register "data[14]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[14]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[13]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "data[12]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[12]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[11]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "data[10]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[10]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[9]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "data[8]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[8]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[7]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "data[6]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[6]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[5]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "data[4]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[4]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[3]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "data[2]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[2]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[1]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "data[0]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "data[0]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "data[15]~reg0" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "data[0]" stuck at VCC
    Warning: Pin "data[1]" stuck at GND
    Warning: Pin "data[2]" stuck at VCC
    Warning: Pin "data[3]" stuck at GND
    Warning: Pin "data[4]" stuck at VCC
    Warning: Pin "data[5]" stuck at GND
    Warning: Pin "data[6]" stuck at VCC
    Warning: Pin "data[7]" stuck at GND
    Warning: Pin "data[8]" stuck at VCC
    Warning: Pin "data[9]" stuck at GND
    Warning: Pin "data[10]" stuck at VCC
    Warning: Pin "data[11]" stuck at GND
    Warning: Pin "data[12]" stuck at VCC
    Warning: Pin "data[13]" stuck at GND
    Warning: Pin "data[14]" stuck at VCC
    Warning: Pin "data[15]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "clk"
Info: Implemented 17 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 16 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
    Info: Processing ended: Tue Jun 06 11:20:24 2006
    Info: Elapsed time: 00:00:03