test.map.summary

很多仪器都输出同步时钟

Flow Status : Successful - Tue Jun 06 11:20:24 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : test
Top-level Entity Name : test
Family : Stratix
Device : EP1S20F484C7
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 0
Total pins : 17
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0