test.vhd

来自「很多仪器都输出同步时钟」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(clk:in std_logic;
    data:out std_logic_vector(15 downto 0));
end test;
architecture bhv of test is
begin
   process(clk)
       begin
          if(clk'event and clk='1')then
                 data<="1111101001011111";
          end if;
end process;
end bhv;