fpgawrite.tan.qmsg

很多仪器都输出同步时钟

{ "Info" "ITDB_TSU_RESULT" "data1\[12\]~reg0 en clk 10.206 ns register " "Info: tsu for register \"data1\[12\]~reg0\" (data pin = \"en\", clock pin = \"clk\") is 10.206 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.131 ns + Longest pin register " "Info: + Longest pin to register delay is 13.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 PIN PIN_53 80 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_53; Fanout = 80; PIN Node = 'en'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "" { en } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(10.795 ns) + CELL(0.867 ns) 13.131 ns data1\[12\]~reg0 2 REG LC_X33_Y20_N5 1 " "Info: 2: + IC(10.795 ns) + CELL(0.867 ns) = 13.131 ns; Loc. = LC_X33_Y20_N5; Fanout = 1; REG Node = 'data1\[12\]~reg0'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "11.662 ns" { en data1[12]~reg0 } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 17.79 % " "Info: Total cell delay = 2.336 ns ( 17.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.795 ns 82.21 % " "Info: Total interconnect delay = 10.795 ns ( 82.21 % )" {  } {  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "13.131 ns" { en data1[12]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.131 ns" { en en~out0 data1[12]~reg0 } { 0.000ns 0.000ns 10.795ns } { 0.000ns 1.469ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 80 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 80; CLK Node = 'clk'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "" { clk } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns data1\[12\]~reg0 2 REG LC_X33_Y20_N5 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X33_Y20_N5; Fanout = 1; REG Node = 'data1\[12\]~reg0'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "1.493 ns" { clk data1[12]~reg0 } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "2.962 ns" { clk data1[12]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 data1[12]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "13.131 ns" { en data1[12]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.131 ns" { en en~out0 data1[12]~reg0 } { 0.000ns 0.000ns 10.795ns } { 0.000ns 1.469ns 0.867ns } } } { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "2.962 ns" { clk data1[12]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 data1[12]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data0\[3\] data0\[3\]~reg0 7.831 ns register " "Info: tco from clock \"clk\" to destination pin \"data0\[3\]\" through register \"data0\[3\]~reg0\" is 7.831 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.910 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 80 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 80; CLK Node = 'clk'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "" { clk } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns data0\[3\]~reg0 2 REG LC_X34_Y8_N0 1 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X34_Y8_N0; Fanout = 1; REG Node = 'data0\[3\]~reg0'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "1.441 ns" { clk data0[3]~reg0 } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "2.910 ns" { clk data0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 data0[3]~reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.697 ns + Longest register pin " "Info: + Longest register to pin delay is 4.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data0\[3\]~reg0 1 REG LC_X34_Y8_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y8_N0; Fanout = 1; REG Node = 'data0\[3\]~reg0'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "" { data0[3]~reg0 } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.573 ns) + CELL(2.124 ns) 4.697 ns data0\[3\] 2 PIN PIN_163 0 " "Info: 2: + IC(2.573 ns) + CELL(2.124 ns) = 4.697 ns; Loc. = PIN_163; Fanout = 0; PIN Node = 'data0\[3\]'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "4.697 ns" { data0[3]~reg0 data0[3] } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 45.22 % " "Info: Total cell delay = 2.124 ns ( 45.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.573 ns 54.78 % " "Info: Total interconnect delay = 2.573 ns ( 54.78 % )" {  } {  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "4.697 ns" { data0[3]~reg0 data0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.697 ns" { data0[3]~reg0 data0[3] } { 0.000ns 2.573ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "2.910 ns" { clk data0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 data0[3]~reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "4.697 ns" { data0[3]~reg0 data0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.697 ns" { data0[3]~reg0 data0[3] } { 0.000ns 2.573ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "data4\[4\]~reg0 fpgatodff4\[4\] clk -1.302 ns register " "Info: th for register \"data4\[4\]~reg0\" (data pin = \"fpgatodff4\[4\]\", clock pin = \"clk\") is -1.302 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.910 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 80 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 80; CLK Node = 'clk'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "" { clk } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns data4\[4\]~reg0 2 REG LC_X34_Y1_N0 1 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X34_Y1_N0; Fanout = 1; REG Node = 'data4\[4\]~reg0'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "1.441 ns" { clk data4[4]~reg0 } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "2.910 ns" { clk data4[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 data4[4]~reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.227 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.227 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fpgatodff4\[4\] 1 PIN PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; PIN Node = 'fpgatodff4\[4\]'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "" { fpgatodff4[4] } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.449 ns) + CELL(0.309 ns) 4.227 ns data4\[4\]~reg0 2 REG LC_X34_Y1_N0 1 " "Info: 2: + IC(2.449 ns) + CELL(0.309 ns) = 4.227 ns; Loc. = LC_X34_Y1_N0; Fanout = 1; REG Node = 'data4\[4\]~reg0'" {  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "2.758 ns" { fpgatodff4[4] data4[4]~reg0 } "NODE_NAME" } "" } } { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 42.06 % " "Info: Total cell delay = 1.778 ns ( 42.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.449 ns 57.94 % " "Info: Total interconnect delay = 2.449 ns ( 57.94 % )" {  } {  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "4.227 ns" { fpgatodff4[4] data4[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.227 ns" { fpgatodff4[4] fpgatodff4[4]~out0 data4[4]~reg0 } { 0.000ns 0.000ns 2.449ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}  } { { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "2.910 ns" { clk data4[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 data4[4]~reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" "" { Report "E:/gytask/fpgawrite1/db/fpgawrite_cmp.qrpt" Compiler "fpgawrite" "UNKNOWN" "V1" "E:/gytask/fpgawrite1/db/fpgawrite.quartus_db" { Floorplan "E:/gytask/fpgawrite1/" "" "4.227 ns" { fpgatodff4[4] data4[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.227 ns" { fpgatodff4[4] fpgatodff4[4]~out0 data4[4]~reg0 } { 0.000ns 0.000ns 2.449ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 09 10:34:11 2006 " "Info: Processing ended: Fri Jun 09 10:34:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}