fpgawrite.vhd

来自「很多仪器都输出同步时钟」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fpgawrite is
port(             clk:in std_logic;
                   en:in std_logic;
           fpgatodff0:in std_logic_vector(15 downto 0);
           fpgatodff1:in std_logic_vector(15 downto 0);
           fpgatodff2:in std_logic_vector(15 downto 0);
           fpgatodff3:in std_logic_vector(15 downto 0);
           fpgatodff4:in std_logic_vector(15 downto 0);
                data0:out std_logic_vector(15 downto 0);
                data1:out std_logic_vector(15 downto 0);
                data2:out std_logic_vector(15 downto 0);
                data3:out std_logic_vector(15 downto 0);
                data4:out std_logic_vector(15 downto 0));     
end fpgawrite;
architecture bhv of fpgawrite  is
begin
a:process(clk)
     begin
             if(clk'event and clk='1')then
                  if(en='1')then
                    data0<=fpgatodff0;
                    data1<=fpgatodff1; 
                    data2<=fpgatodff2; 
                    data3<=fpgatodff3; 
                    data4<=fpgatodff4;
                   end if; 
              end if;
end process a; 
end bhv;