bjq.map.rpt

很多仪器都输出同步时钟

; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 16 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |bjq|Mux~16                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/gytask/interface/bjq.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 09 11:18:14 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bjq -c bjq
Info: Found 2 design units, including 1 entities, in source file bjq.vhd
    Info: Found design unit 1: bjq-bhv
    Info: Found entity 1: bjq
Info: Found 1 design units, including 1 entities, in source file bjq11.bdf
    Info: Found entity 1: bjq11
Info: Elaborating entity "bjq" for the top level hierarchy
Warning: VHDL Process Statement warning at bjq.vhd(21): signal "ce" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(23): signal "rd" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(61): signal "s" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(62): signal "dfftodsp0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(63): signal "dfftodsp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(64): signal "dfftodsp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(65): signal "dfftodsp3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(66): signal "dfftodsp4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable "ren0" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ren0" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable "ren1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ren1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable "ren2" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ren2" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable "ren3" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ren3" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable "ren4" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ren4" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable "ren5" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ren5" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at bjq.vhd(19): signal or variable "ed" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ed" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Replaced VCC/GND feeding tri-state bus ren1~0 with an always-enabled tri-state buffer
Warning: Replaced VCC/GND feeding tri-state bus ren2~0 with an always-enabled tri-state buffer
Warning: Replaced VCC/GND feeding tri-state bus ren3~0 with an always-enabled tri-state buffer
Warning: Replaced VCC/GND feeding tri-state bus ren4~0 with an always-enabled tri-state buffer
Warning: Replaced VCC/GND feeding tri-state bus ren0~0 with an always-enabled tri-state buffer
Warning: Replaced VCC/GND feeding tri-state bus ren5~0 with an always-enabled tri-state buffer
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ren1" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ren2" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ren3" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ren4" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ren0" is moved to its source
Warning: TRI or OPNDRN buffers permanently disabled
    Warning: Node "a~17"
    Warning: Node "a~16"
    Warning: Node "a~15"
    Warning: Node "a~14"
    Warning: Node "a~13"
    Warning: Node "a~12"
    Warning: Node "a~11"
    Warning: Node "a~10"
    Warning: Node "a~9"
    Warning: Node "a~8"
    Warning: Node "a~7"
    Warning: Node "a~6"
    Warning: Node "a~5"
    Warning: Node "a~4"
    Warning: Node "a~3"
    Warning: Node "a~2"
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "ren1~1"
    Warning: Node "ren2~1"
    Warning: Node "ren3~1"
    Warning: Node "ren4~1"
    Warning: Node "ren0~1"
Warning: Design contains 80 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "ea[0]"
    Warning: No output dependent on input pin "ea[1]"
    Warning: No output dependent on input pin "ea[2]"
    Warning: No output dependent on input pin "ea[3]"
    Warning: No output dependent on input pin "ea[4]"
    Warning: No output dependent on input pin "ea[5]"
    Warning: No output dependent on input pin "ea[6]"
    Warning: No output dependent on input pin "ea[7]"
    Warning: No output dependent on input pin "ea[8]"
    Warning: No output dependent on input pin "ea[9]"
    Warning: No output dependent on input pin "ea[10]"
    Warning: No output dependent on input pin "ea[11]"
    Warning: No output dependent on input pin "ea[12]"
    Warning: No output dependent on input pin "ea[13]"
    Warning: No output dependent on input pin "ea[14]"
    Warning: No output dependent on input pin "ea[15]"
    Warning: No output dependent on input pin "dfftodsp2[0]"
    Warning: No output dependent on input pin "dfftodsp3[0]"
    Warning: No output dependent on input pin "dfftodsp4[0]"
    Warning: No output dependent on input pin "dfftodsp1[0]"
    Warning: No output dependent on input pin "dfftodsp3[1]"
    Warning: No output dependent on input pin "dfftodsp2[1]"
    Warning: No output dependent on input pin "dfftodsp4[1]"
    Warning: No output dependent on input pin "dfftodsp1[1]"
    Warning: No output dependent on input pin "dfftodsp2[2]"
    Warning: No output dependent on input pin "dfftodsp3[2]"
    Warning: No output dependent on input pin "dfftodsp4[2]"
    Warning: No output dependent on input pin "dfftodsp1[2]"
    Warning: No output dependent on input pin "dfftodsp3[3]"
    Warning: No output dependent on input pin "dfftodsp2[3]"
    Warning: No output dependent on input pin "dfftodsp4[3]"
    Warning: No output dependent on input pin "dfftodsp1[3]"
    Warning: No output dependent on input pin "dfftodsp2[4]"
    Warning: No output dependent on input pin "dfftodsp3[4]"
    Warning: No output dependent on input pin "dfftodsp4[4]"
    Warning: No output dependent on input pin "dfftodsp1[4]"
    Warning: No output dependent on input pin "dfftodsp3[5]"
    Warning: No output dependent on input pin "dfftodsp2[5]"
    Warning: No output dependent on input pin "dfftodsp4[5]"
    Warning: No output dependent on input pin "dfftodsp1[5]"
    Warning: No output dependent on input pin "dfftodsp2[6]"
    Warning: No output dependent on input pin "dfftodsp3[6]"
    Warning: No output dependent on input pin "dfftodsp4[6]"
    Warning: No output dependent on input pin "dfftodsp1[6]"
    Warning: No output dependent on input pin "dfftodsp3[7]"
    Warning: No output dependent on input pin "dfftodsp2[7]"
    Warning: No output dependent on input pin "dfftodsp4[7]"
    Warning: No output dependent on input pin "dfftodsp1[7]"
    Warning: No output dependent on input pin "dfftodsp2[8]"
    Warning: No output dependent on input pin "dfftodsp3[8]"
    Warning: No output dependent on input pin "dfftodsp4[8]"
    Warning: No output dependent on input pin "dfftodsp1[8]"
    Warning: No output dependent on input pin "dfftodsp3[9]"
    Warning: No output dependent on input pin "dfftodsp2[9]"
    Warning: No output dependent on input pin "dfftodsp4[9]"
    Warning: No output dependent on input pin "dfftodsp1[9]"
    Warning: No output dependent on input pin "dfftodsp2[10]"
    Warning: No output dependent on input pin "dfftodsp3[10]"
    Warning: No output dependent on input pin "dfftodsp4[10]"
    Warning: No output dependent on input pin "dfftodsp1[10]"
    Warning: No output dependent on input pin "dfftodsp3[11]"
    Warning: No output dependent on input pin "dfftodsp2[11]"
    Warning: No output dependent on input pin "dfftodsp4[11]"
    Warning: No output dependent on input pin "dfftodsp1[11]"
    Warning: No output dependent on input pin "dfftodsp2[12]"
    Warning: No output dependent on input pin "dfftodsp3[12]"
    Warning: No output dependent on input pin "dfftodsp4[12]"
    Warning: No output dependent on input pin "dfftodsp1[12]"
    Warning: No output dependent on input pin "dfftodsp3[13]"
    Warning: No output dependent on input pin "dfftodsp2[13]"
    Warning: No output dependent on input pin "dfftodsp4[13]"
    Warning: No output dependent on input pin "dfftodsp1[13]"
    Warning: No output dependent on input pin "dfftodsp2[14]"
    Warning: No output dependent on input pin "dfftodsp3[14]"
    Warning: No output dependent on input pin "dfftodsp4[14]"
    Warning: No output dependent on input pin "dfftodsp1[14]"
    Warning: No output dependent on input pin "dfftodsp3[15]"
    Warning: No output dependent on input pin "dfftodsp2[15]"
    Warning: No output dependent on input pin "dfftodsp4[15]"
    Warning: No output dependent on input pin "dfftodsp1[15]"
Info: Implemented 137 device resources after synthesis - the final resource count might be different
    Info: Implemented 98 input pins
    Info: Implemented 0 output pins
    Info: Implemented 22 bidirectional pins
    Info: Implemented 17 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 125 warnings
    Info: Processing ended: Fri Jun 09 11:18:18 2006
    Info: Elapsed time: 00:00:05