📄 bjq.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bjq is
port( ce,rd:in std_logic;
ea:in std_logic_vector(15 downto 0);
ed:inout std_logic_vector(15 downto 0);
ren1,ren2,ren3,ren4,ren0,ren5:inout std_logic:='0';
dfftodsp0:in std_logic_vector(15 downto 0);
dfftodsp1:in std_logic_vector(15 downto 0);
dfftodsp2:in std_logic_vector(15 downto 0);
dfftodsp3:in std_logic_vector(15 downto 0);
dfftodsp4:in std_logic_vector(15 downto 0));
end bjq;
architecture bhv of bjq is
signal s:std_logic_vector(4 downto 0);
begin
s<=ren4&ren3&ren2&ren1&ren0;
a: process(ea)
begin
if(ce='0')then
if(rd='0')then
--case ea is
-- when "0100000000000000"=>ren0<='1';
-- when "0100000000000001"=>ren1<='1';
-- when "0100000000000010"=>ren2<='1';
-- when "0100000000000011"=>ren3<='1';
-- when "0100000000000100"=>ren4<='1';
-- when OTHERS=>ren5<='0';
--end case;
-- ed<="1010010110100101";
-- if(ren0='1')then
-- ed<=dfftodsp0;
-- elsif(ren0='1')then
-- ed<=dfftodsp1;
-- elsif(ren0='1')then
-- ed<=dfftodsp2;
-- elsif(ren0='1')then
-- ed<=dfftodsp3;
-- elsif(ren0='1')then
-- ed<=dfftodsp4;
-- else
-- ed<=(others=>'Z');
-- end if;
if(ea="1000000000000000")then
ren0<='1';
elsif(ea="1000000000000001")then
ren1<='1';
elsif(ea="1000000000000010")then
ren2<='1';
elsif(ea="1000000000000011")then
ren3<='1';
elsif(ea="1000000000000100")then
ren4<='1';
else
ren5<='0';
end if;
case s is
when"00001"=>ed<=dfftodsp0;
when"00010"=>ed<=dfftodsp1;
when"00100"=>ed<=dfftodsp2;
when"01000"=>ed<=dfftodsp3;
when"10000"=>ed<=dfftodsp4;
when others=>ed<=(others=>'Z');
end case;
end if;
end if;
end process;
end bhv;
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