tx_data.vhd

很多仪器都输出同步时钟

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tx_data is
       Port (clk,enable:in std_logic;
             data_in:in std_logic_vector(7 downto 0);
             data_val:in std_logic;
             tx:out std_logic
             );
end tx_data;

    
architecture Behavioral of tx_data is   
signal tx_en,tx_t:std_logic;
signal data_count:integer range 0 to 3000;
signal tx_count:std_logic_vector(3 downto 0);
signal data:std_logic_vector(7 downto 0);
constant BIT_RATE:integer:=216;
begin

process(clk)
begin
if(tx_count=10) then
	tx_en<='0';
elsif(data_val'event and data_val='1') then
   if (enable='1') then
	tx_en<='1';
   end if;
end if;
end process;

process(clk)
begin
if(tx_en='0') then
	data_count<=0;
elsif(clk'event and clk='1') then
	if(data_count=BIT_RATE) then
		data_count<=0;
	else
		data_count<=data_count+1;
	end if;
end if;
end process;

process(clk)
begin
if(clk'event and clk='1') then
    if(tx_en='0') then
        tx_count<="0000";
	elsif(data_count=BIT_RATE) then
		tx_count<=tx_count+'1';
	end if;
end if;
end process;

process(data_val)
begin
if(data_val'event and data_val='1') then
	data<=data_in;
end if;
end process;

tx<='0'     when tx_en='1' and tx_count=0 else
    data(0) when tx_en='1' and tx_count=1 else
    data(1) when tx_en='1' and tx_count=2 else
    data(2) when tx_en='1' and tx_count=3 else
    data(3) when tx_en='1' and tx_count=4 else
    data(4) when tx_en='1' and tx_count=5 else
    data(5) when tx_en='1' and tx_count=6 else
    data(6) when tx_en='1' and tx_count=7 else
    data(7) when tx_en='1' and tx_count=8 else
    '1';

end Behavioral;