fspi.map.qmsg

很多仪器都输出同步时钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 25 10:48:09 2006 " "Info: Processing started: Sun Jun 25 10:48:09 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Fspi -c Fspi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Fspi -c Fspi" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../send_package.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file ../../send_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SEND_PACKAGE " "Info: Found design unit 1: SEND_PACKAGE" {  } { { "../../send_package.vhd" "" { Text "D:/spi/send/send_package.vhd" 6 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 SEND_PACKAGE-body " "Info: Found design unit 2: SEND_PACKAGE-body" {  } { { "../../send_package.vhd" "" { Text "D:/spi/send/send_package.vhd" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DALITEST.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DALITEST.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DALITEST-rtl " "Info: Found design unit 1: DALITEST-rtl" {  } { { "DALITEST.vhd" "" { Text "D:/spi/send/spi backup/Fspi/DALITEST.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DALITEST " "Info: Found entity 1: DALITEST" {  } { { "DALITEST.vhd" "" { Text "D:/spi/send/spi backup/Fspi/DALITEST.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../recv/recv_package.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file ../../../recv/recv_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RECV_PACKAGE " "Info: Found design unit 1: RECV_PACKAGE" {  } { { "../../../recv/recv_package.vhd" "" { Text "D:/spi/recv/recv_package.vhd" 6 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 RECV_PACKAGE-body " "Info: Found design unit 2: RECV_PACKAGE-body" {  } { { "../../../recv/recv_package.vhd" "" { Text "D:/spi/recv/recv_package.vhd" 38 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/spi/send/send/send_package.vhd " "Warning: Can't analyze file -- file D:/spi/send/send/send_package.vhd is missing" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fifo0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fifo0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fifo0-SYN " "Info: Found design unit 1: fifo0-SYN" {  } { { "fifo0.vhd" "" { Text "D:/spi/send/spi backup/Fspi/fifo0.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fifo0 " "Info: Found entity 1: fifo0" {  } { { "fifo0.vhd" "" { Text "D:/spi/send/spi backup/Fspi/fifo0.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Fspi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Fspi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fspi-rtl " "Info: Found design unit 1: fspi-rtl" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 22 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fspi " "Info: Found entity 1: fspi" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file spi.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 spi " "Info: Found entity 1: spi" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_data.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tx_data.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_data-Behavioral " "Info: Found design unit 1: tx_data-Behavioral" {  } { { "tx_data.vhd" "" { Text "D:/spi/send/spi backup/Fspi/tx_data.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 tx_data " "Info: Found entity 1: tx_data" {  } { { "tx_data.vhd" "" { Text "D:/spi/send/spi backup/Fspi/tx_data.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "syn_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file syn_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 syn_gen-rtl " "Info: Found design unit 1: syn_gen-rtl" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 syn_gen " "Info: Found entity 1: syn_gen" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "spi " "Info: Elaborating entity \"spi\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "wrreq fifo0 inst1 " "Warning: Port \"wrreq\" of type fifo0 and instance \"inst1\" is missing source signal" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 320 144 304 488 "inst1" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "wrclk fifo0 inst1 " "Warning: Port \"wrclk\" of type fifo0 and instance \"inst1\" is missing source signal" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 320 144 304 488 "inst1" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "data fifo0 inst1 " "Warning: Port \"data\" of type fifo0 and instance \"inst1\" is missing source signal" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 320 144 304 488 "inst1" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "wrfull fspi inst " "Warning: Port \"wrfull\" of type fspi and instance \"inst\" is missing source signal" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 264 584 776 584 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "tx485_in1 " "Warning: Pin \"tx485_in1\" not connected" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1408 120 288 1424 "tx485_in1" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "en485_in1 " "Warning: Pin \"en485_in1\" not connected" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1384 120 288 1400 "en485_in1" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "en485_in2 " "Warning: Pin \"en485_in2\" not connected" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1280 136 304 1296 "en485_in2" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "tx485_in2 " "Warning: Pin \"tx485_in2\" not connected" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1296 136 304 1312 "tx485_in2" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fspi fspi:inst " "Info: Elaborating entity \"fspi\" for hierarchy \"fspi:inst\"" {  } { { "spi.bdf" "inst" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 264 584 776 584 "inst" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clkcount1 Fspi.vhd(26) " "Info: (10035) Verilog HDL or VHDL information at Fspi.vhd(26): object \"clkcount1\" declared but not used" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count Fspi.vhd(51) " "Warning: VHDL Process Statement warning at Fspi.vhd(51): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count Fspi.vhd(54) " "Warning: VHDL Process Statement warning at Fspi.vhd(54): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fiforead Fspi.vhd(54) " "Warning: VHDL Process Statement warning at Fspi.vhd(54): signal \"fiforead\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count Fspi.vhd(67) " "Warning: VHDL Process Statement warning at Fspi.vhd(67): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "fiforead Fspi.vhd(49) " "Warning: VHDL Process Statement warning at Fspi.vhd(49): signal or variable \"fiforead\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"fiforead\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "clkout Fspi.vhd(49) " "Warning: VHDL Process Statement warning at Fspi.vhd(49): signal or variable \"clkout\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"clkout\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "spiclk Fspi.vhd(76) " "Warning: VHDL Process Statement warning at Fspi.vhd(76): signal \"spiclk\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 76 0 0 } }  } 0}