fspi.fit.qmsg

很多仪器都输出同步时钟

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|cout Global clock " "Info: Automatically promoted signal \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|cout\" to use Global clock" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 106 2 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "syn_in Global clock " "Info: Automatically promoted signal \"syn_in\" to use Global clock" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1032 120 288 1048 "syn_in" "" } { 1024 288 344 1040 "syn_in" "" } { 1520 752 840 1536 "syn_in" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "syn_in " "Info: Pin \"syn_in\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1032 120 288 1048 "syn_in" "" } { 1024 288 344 1040 "syn_in" "" } { 1520 752 840 1536 "syn_in" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "syn_in" } } } } { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "" { syn_in } "NODE_NAME" } "" } } { "D:/spi/send/spi backup/Fspi/Fspi.fld" "" { Floorplan "D:/spi/send/spi backup/Fspi/Fspi.fld" "" "" { syn_in } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "syn_gen:inst2\|syn_out Global clock " "Info: Automatically promoted some destinations of signal \"syn_gen:inst2\|syn_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SYN " "Info: Destination \"SYN\" may be non-global or may not use global clock" {  } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1072 640 816 1088 "SYN" "" } { 1640 616 672 1656 "syn" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[3\] " "Info: Destination \"syn_gen:inst2\|syn_count\[3\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[0\] " "Info: Destination \"syn_gen:inst2\|syn_count\[0\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[1\] " "Info: Destination \"syn_gen:inst2\|syn_count\[1\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[2\] " "Info: Destination \"syn_gen:inst2\|syn_count\[2\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[5\] " "Info: Destination \"syn_gen:inst2\|syn_count\[5\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[7\] " "Info: Destination \"syn_gen:inst2\|syn_count\[7\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[4\] " "Info: Destination \"syn_gen:inst2\|syn_count\[4\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[6\] " "Info: Destination \"syn_gen:inst2\|syn_count\[6\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "syn_gen:inst2\|syn_count\[8\] " "Info: Destination \"syn_gen:inst2\|syn_count\[8\]\" may be non-global or may not use global clock" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 3.30 0 7 0 " "Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 0 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 11 33 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used --  33 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 4 44 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  44 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 23 26 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 23 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 39 9 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 39 total pin(s) used --  9 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_miu:auto_generated\|altsyncram_p3v:fifo_ram\|ram_block9a0 clk0 GND " "Warning: WYSIWYG primitive \"fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_miu:auto_generated\|altsyncram_p3v:fifo_ram\|ram_block9a0\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_p3v.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/altsyncram_p3v.tdf" 42 2 0 } } { "db/dcfifo_miu.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/dcfifo_miu.tdf" 68 2 0 } } { "dcfifo.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/dcfifo.tdf" 185 2 0 } } { "fifo0.vhd" "" { Text "D:/spi/send/spi backup/Fspi/fifo0.vhd" 93 -1 0 } } { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 320 144 304 488 "inst1" "" } } } }  } 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_miu:auto_generated\|altsyncram_p3v:fifo_ram\|ram_block9a4 clk0 GND " "Warning: WYSIWYG primitive \"fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_miu:auto_generated\|altsyncram_p3v:fifo_ram\|ram_block9a4\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_p3v.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/altsyncram_p3v.tdf" 42 2 0 } } { "db/dcfifo_miu.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/dcfifo_miu.tdf" 68 2 0 } } { "dcfifo.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/dcfifo.tdf" 185 2 0 } } { "fifo0.vhd" "" { Text "D:/spi/send/spi backup/Fspi/fifo0.vhd" 93 -1 0 } } { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 320 144 304 488 "inst1" "" } } } }  } 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_miu:auto_generated\|altsyncram_p3v:fifo_ram\|ram_block9a5 clk0 GND " "Warning: WYSIWYG primitive \"fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_miu:auto_generated\|altsyncram_p3v:fifo_ram\|ram_block9a5\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_p3v.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/altsyncram_p3v.tdf" 42 2 0 } } { "db/dcfifo_miu.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/dcfifo_miu.tdf" 68 2 0 } } { "dcfifo.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/dcfifo.tdf" 185 2 0 } } { "fifo0.vhd" "" { Text "D:/spi/send/spi backup/Fspi/fifo0.vhd" 93 -1 0 } } { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 320 144 304 488 "inst1" "" } } } }  } 0}