fspi.hier_info

很多仪器都输出同步时钟

q[50] <= dcfifo_miu:auto_generated.q[50]
q[51] <= dcfifo_miu:auto_generated.q[51]
q[52] <= dcfifo_miu:auto_generated.q[52]
q[53] <= dcfifo_miu:auto_generated.q[53]
q[54] <= dcfifo_miu:auto_generated.q[54]
q[55] <= dcfifo_miu:auto_generated.q[55]
q[56] <= dcfifo_miu:auto_generated.q[56]
q[57] <= dcfifo_miu:auto_generated.q[57]
q[58] <= dcfifo_miu:auto_generated.q[58]
q[59] <= dcfifo_miu:auto_generated.q[59]
q[60] <= dcfifo_miu:auto_generated.q[60]
q[61] <= dcfifo_miu:auto_generated.q[61]
q[62] <= dcfifo_miu:auto_generated.q[62]
q[63] <= dcfifo_miu:auto_generated.q[63]
rdclk => dcfifo_miu:auto_generated.rdclk
rdreq => dcfifo_miu:auto_generated.rdreq
wrclk => dcfifo_miu:auto_generated.wrclk
wrreq => dcfifo_miu:auto_generated.wrreq
aclr => ~NO_FANOUT~
rdempty <= dcfifo_miu:auto_generated.rdempty
rdfull <= <GND>
wrempty <= <GND>
wrfull <= dcfifo_miu:auto_generated.wrfull
rdusedw[0] <= <GND>
rdusedw[1] <= <GND>
rdusedw[2] <= <GND>
rdusedw[3] <= <GND>
rdusedw[4] <= <GND>
rdusedw[5] <= <GND>
rdusedw[6] <= <GND>
rdusedw[7] <= <GND>
wrusedw[0] <= <GND>
wrusedw[1] <= <GND>
wrusedw[2] <= <GND>
wrusedw[3] <= <GND>
wrusedw[4] <= <GND>
wrusedw[5] <= <GND>
wrusedw[6] <= <GND>
wrusedw[7] <= <GND>


|spi|fifo0:inst1|dcfifo:dcfifo_component|dcfifo_miu:auto_generated
data[0] => altsyncram_p3v:fifo_ram.data_a[0]
data[1] => altsyncram_p3v:fifo_ram.data_a[1]
data[2] => altsyncram_p3v:fifo_ram.data_a[2]
data[3] => altsyncram_p3v:fifo_ram.data_a[3]
data[4] => altsyncram_p3v:fifo_ram.data_a[4]
data[5] => altsyncram_p3v:fifo_ram.data_a[5]
data[6] => altsyncram_p3v:fifo_ram.data_a[6]
data[7] => altsyncram_p3v:fifo_ram.data_a[7]
data[8] => altsyncram_p3v:fifo_ram.data_a[8]
data[9] => altsyncram_p3v:fifo_ram.data_a[9]
data[10] => altsyncram_p3v:fifo_ram.data_a[10]
data[11] => altsyncram_p3v:fifo_ram.data_a[11]
data[12] => altsyncram_p3v:fifo_ram.data_a[12]
data[13] => altsyncram_p3v:fifo_ram.data_a[13]
data[14] => altsyncram_p3v:fifo_ram.data_a[14]
data[15] => altsyncram_p3v:fifo_ram.data_a[15]
data[16] => altsyncram_p3v:fifo_ram.data_a[16]
data[17] => altsyncram_p3v:fifo_ram.data_a[17]
data[18] => altsyncram_p3v:fifo_ram.data_a[18]
data[19] => altsyncram_p3v:fifo_ram.data_a[19]
data[20] => altsyncram_p3v:fifo_ram.data_a[20]
data[21] => altsyncram_p3v:fifo_ram.data_a[21]
data[22] => altsyncram_p3v:fifo_ram.data_a[22]
data[23] => altsyncram_p3v:fifo_ram.data_a[23]
data[24] => altsyncram_p3v:fifo_ram.data_a[24]
data[25] => altsyncram_p3v:fifo_ram.data_a[25]
data[26] => altsyncram_p3v:fifo_ram.data_a[26]
data[27] => altsyncram_p3v:fifo_ram.data_a[27]
data[28] => altsyncram_p3v:fifo_ram.data_a[28]
data[29] => altsyncram_p3v:fifo_ram.data_a[29]
data[30] => altsyncram_p3v:fifo_ram.data_a[30]
data[31] => altsyncram_p3v:fifo_ram.data_a[31]
data[32] => altsyncram_p3v:fifo_ram.data_a[32]
data[33] => altsyncram_p3v:fifo_ram.data_a[33]
data[34] => altsyncram_p3v:fifo_ram.data_a[34]
data[35] => altsyncram_p3v:fifo_ram.data_a[35]
data[36] => altsyncram_p3v:fifo_ram.data_a[36]
data[37] => altsyncram_p3v:fifo_ram.data_a[37]
data[38] => altsyncram_p3v:fifo_ram.data_a[38]
data[39] => altsyncram_p3v:fifo_ram.data_a[39]
data[40] => altsyncram_p3v:fifo_ram.data_a[40]
data[41] => altsyncram_p3v:fifo_ram.data_a[41]
data[42] => altsyncram_p3v:fifo_ram.data_a[42]
data[43] => altsyncram_p3v:fifo_ram.data_a[43]
data[44] => altsyncram_p3v:fifo_ram.data_a[44]
data[45] => altsyncram_p3v:fifo_ram.data_a[45]
data[46] => altsyncram_p3v:fifo_ram.data_a[46]
data[47] => altsyncram_p3v:fifo_ram.data_a[47]
data[48] => altsyncram_p3v:fifo_ram.data_a[48]
data[49] => altsyncram_p3v:fifo_ram.data_a[49]
data[50] => altsyncram_p3v:fifo_ram.data_a[50]
data[51] => altsyncram_p3v:fifo_ram.data_a[51]
data[52] => altsyncram_p3v:fifo_ram.data_a[52]
data[53] => altsyncram_p3v:fifo_ram.data_a[53]
data[54] => altsyncram_p3v:fifo_ram.data_a[54]
data[55] => altsyncram_p3v:fifo_ram.data_a[55]
data[56] => altsyncram_p3v:fifo_ram.data_a[56]
data[57] => altsyncram_p3v:fifo_ram.data_a[57]
data[58] => altsyncram_p3v:fifo_ram.data_a[58]
data[59] => altsyncram_p3v:fifo_ram.data_a[59]
data[60] => altsyncram_p3v:fifo_ram.data_a[60]
data[61] => altsyncram_p3v:fifo_ram.data_a[61]
data[62] => altsyncram_p3v:fifo_ram.data_a[62]
data[63] => altsyncram_p3v:fifo_ram.data_a[63]
q[0] <= scfifo:output_channel.q[0]
q[1] <= scfifo:output_channel.q[1]
q[2] <= scfifo:output_channel.q[2]
q[3] <= scfifo:output_channel.q[3]
q[4] <= scfifo:output_channel.q[4]
q[5] <= scfifo:output_channel.q[5]
q[6] <= scfifo:output_channel.q[6]
q[7] <= scfifo:output_channel.q[7]
q[8] <= scfifo:output_channel.q[8]
q[9] <= scfifo:output_channel.q[9]
q[10] <= scfifo:output_channel.q[10]
q[11] <= scfifo:output_channel.q[11]
q[12] <= scfifo:output_channel.q[12]
q[13] <= scfifo:output_channel.q[13]
q[14] <= scfifo:output_channel.q[14]
q[15] <= scfifo:output_channel.q[15]
q[16] <= scfifo:output_channel.q[16]
q[17] <= scfifo:output_channel.q[17]
q[18] <= scfifo:output_channel.q[18]
q[19] <= scfifo:output_channel.q[19]
q[20] <= scfifo:output_channel.q[20]
q[21] <= scfifo:output_channel.q[21]
q[22] <= scfifo:output_channel.q[22]
q[23] <= scfifo:output_channel.q[23]
q[24] <= scfifo:output_channel.q[24]
q[25] <= scfifo:output_channel.q[25]
q[26] <= scfifo:output_channel.q[26]
q[27] <= scfifo:output_channel.q[27]
q[28] <= scfifo:output_channel.q[28]
q[29] <= scfifo:output_channel.q[29]
q[30] <= scfifo:output_channel.q[30]
q[31] <= scfifo:output_channel.q[31]
q[32] <= scfifo:output_channel.q[32]
q[33] <= scfifo:output_channel.q[33]
q[34] <= scfifo:output_channel.q[34]
q[35] <= scfifo:output_channel.q[35]
q[36] <= scfifo:output_channel.q[36]
q[37] <= scfifo:output_channel.q[37]
q[38] <= scfifo:output_channel.q[38]
q[39] <= scfifo:output_channel.q[39]
q[40] <= scfifo:output_channel.q[40]
q[41] <= scfifo:output_channel.q[41]
q[42] <= scfifo:output_channel.q[42]
q[43] <= scfifo:output_channel.q[43]
q[44] <= scfifo:output_channel.q[44]
q[45] <= scfifo:output_channel.q[45]
q[46] <= scfifo:output_channel.q[46]
q[47] <= scfifo:output_channel.q[47]
q[48] <= scfifo:output_channel.q[48]
q[49] <= scfifo:output_channel.q[49]
q[50] <= scfifo:output_channel.q[50]
q[51] <= scfifo:output_channel.q[51]
q[52] <= scfifo:output_channel.q[52]
q[53] <= scfifo:output_channel.q[53]
q[54] <= scfifo:output_channel.q[54]
q[55] <= scfifo:output_channel.q[55]
q[56] <= scfifo:output_channel.q[56]
q[57] <= scfifo:output_channel.q[57]
q[58] <= scfifo:output_channel.q[58]
q[59] <= scfifo:output_channel.q[59]
q[60] <= scfifo:output_channel.q[60]
q[61] <= scfifo:output_channel.q[61]
q[62] <= scfifo:output_channel.q[62]
q[63] <= scfifo:output_channel.q[63]
rdclk => a_graycounter_i06:rdptr_g.clock
rdclk => a_graycounter_j06:read_counter_for_write.clock
rdclk => altsyncram_p3v:fifo_ram.clock1
rdclk => alt_synch_pipe_2a3:read_sync_registers.clock
rdclk => cntr_uu7:rdptr_b.clock
rdclk => scfifo:output_channel.clock
rdclk => dffe6a[7].CLK
rdclk => dffe6a[6].CLK
rdclk => dffe6a[5].CLK
rdclk => dffe6a[4].CLK
rdclk => dffe6a[3].CLK
rdclk => dffe6a[2].CLK
rdclk => dffe6a[1].CLK
rdclk => dffe6a[0].CLK
rdclk => dffe7a[7].CLK
rdclk => dffe7a[6].CLK
rdclk => dffe7a[5].CLK
rdclk => dffe7a[4].CLK
rdclk => dffe7a[3].CLK
rdclk => dffe7a[2].CLK
rdclk => dffe7a[1].CLK
rdclk => dffe7a[0].CLK
rdclk => dffe8a[7].CLK
rdclk => dffe8a[6].CLK
rdclk => dffe8a[5].CLK
rdclk => dffe8a[4].CLK
rdclk => dffe8a[3].CLK
rdclk => dffe8a[2].CLK
rdclk => dffe8a[1].CLK
rdclk => dffe8a[0].CLK
rdclk => fifo_wreq_pipe[1].CLK
rdclk => fifo_wreq_pipe[0].CLK
rdclk => rdfull_delay.CLK
rdempty <= pre_rdempty.DB_MAX_OUTPUT_PORT_TYPE
rdfull <= rdfull_delay.DB_MAX_OUTPUT_PORT_TYPE
rdreq => scfifo:output_channel.rdreq
rdreq => valid_rreq.IN0
rdusedw[0] <= dffe8a[0].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[1] <= dffe8a[1].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[2] <= dffe8a[2].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[3] <= dffe8a[3].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[4] <= dffe8a[4].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[5] <= dffe8a[5].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[6] <= dffe8a[6].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[7] <= dffe8a[7].DB_MAX_OUTPUT_PORT_TYPE
wrclk => a_graycounter_i06:wrptr_g.clock
wrclk => altsyncram_p3v:fifo_ram.clock0
wrclk => alt_synch_pipe_3a3:write_sync_registers.clock
wrclk => cntr_uu7:wrptr_b.clock
wrclk => delayed_wrptr_g[7].CLK
wrclk => delayed_wrptr_g[6].CLK
wrclk => delayed_wrptr_g[5].CLK
wrclk => delayed_wrptr_g[4].CLK
wrclk => delayed_wrptr_g[3].CLK
wrclk => delayed_wrptr_g[2].CLK
wrclk => delayed_wrptr_g[1].CLK
wrclk => delayed_wrptr_g[0].CLK
wrclk => dffe2a[7].CLK
wrclk => dffe2a[6].CLK
wrclk => dffe2a[5].CLK
wrclk => dffe2a[4].CLK
wrclk => dffe2a[3].CLK
wrclk => dffe2a[2].CLK
wrclk => dffe2a[1].CLK
wrclk => dffe2a[0].CLK
wrclk => dffe3a[7].CLK
wrclk => dffe3a[6].CLK
wrclk => dffe3a[5].CLK
wrclk => dffe3a[4].CLK
wrclk => dffe3a[3].CLK
wrclk => dffe3a[2].CLK
wrclk => dffe3a[1].CLK
wrclk => dffe3a[0].CLK
wrclk => dffe4a[7].CLK
wrclk => dffe4a[6].CLK
wrclk => dffe4a[5].CLK
wrclk => dffe4a[4].CLK
wrclk => dffe4a[3].CLK
wrclk => dffe4a[2].CLK
wrclk => dffe4a[1].CLK
wrclk => dffe4a[0].CLK
wrclk => lwrreq.CLK
wrclk => wrempty_delay.CLK
wrclk => wrfull_delay.CLK
wrfull <= wrfull_delay.DB_MAX_OUTPUT_PORT_TYPE
wrreq => valid_wrreq.IN1
wrreq => lwrreq.DATAIN
wrusedw[0] <= dffe4a[0].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[1] <= dffe4a[1].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[2] <= dffe4a[2].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[3] <= dffe4a[3].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[4] <= dffe4a[4].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[5] <= dffe4a[5].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[6] <= dffe4a[6].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[7] <= dffe4a[7].DB_MAX_OUTPUT_PORT_TYPE


|spi|fifo0:inst1|dcfifo:dcfifo_component|dcfifo_miu:auto_generated|a_gray2bin_p4b:read_side_gray_converter
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN0
gray[6] => xor6.IN1
gray[7] => bin[7].DATAIN
gray[7] => xor6.IN0


|spi|fifo0:inst1|dcfifo:dcfifo_component|dcfifo_miu:auto_generated|a_gray2bin_p4b:write_side_gray_converter
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN0
gray[6] => xor6.IN1
gray[7] => bin[7].DATAIN
gray[7] => xor6.IN0


|spi|fifo0:inst1|dcfifo:dcfifo_component|dcfifo_miu:auto_generated|a_graycounter_i06:rdptr_g
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => parity.ACLR
clk_en => countera0.ENA
clk_en => countera1.ENA
clk_en => countera2.ENA
clk_en => countera3.ENA
clk_en => countera4.ENA
clk_en => countera5.ENA
clk_en => countera6.ENA
clk_en => countera7.ENA
clk_en => parity.ENA
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => parity.CLK
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT


|spi|fifo0:inst1|dcfifo:dcfifo_component|dcfifo_miu:auto_generated|a_graycounter_j06:read_counter_for_write
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => parity.ACLR
clk_en => countera0.ENA
clk_en => countera1.ENA
clk_en => countera2.ENA
clk_en => countera3.ENA
clk_en => countera4.ENA