fspi.tan.qmsg

很多仪器都输出同步时钟

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "26 " "Warning: Found 26 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[0\] " "Info: Detected ripple clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[0\]\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 78 8 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella1~COUTCOUT1 " "Info: Detected gated clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella1~COUTCOUT1\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 39 2 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella1~COUTCOUT1" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[1\] " "Info: Detected ripple clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[1\]\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 78 8 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[1\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella1~COUT " "Info: Detected gated clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella1~COUT\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 39 2 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella1~COUT" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[2\] " "Info: Detected ripple clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[2\]\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 78 8 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[2\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella2~COUTCOUT1_1 " "Info: Detected gated clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella2~COUTCOUT1_1\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 47 2 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella2~COUTCOUT1_1" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella2~COUT " "Info: Detected gated clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella2~COUT\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 47 2 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella2~COUT" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[3\] " "Info: Detected ripple clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[3\]\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 78 8 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|safe_q\[3\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella3~COUTCOUT1_1 " "Info: Detected gated clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella3~COUTCOUT1_1\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 55 2 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella3~COUTCOUT1_1" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella3~COUT " "Info: Detected gated clock \"lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella3~COUT\" as buffer" {  } { { "db/cntr_7b7.tdf" "" { Text "D:/spi/send/spi backup/Fspi/db/cntr_7b7.tdf" 55 2 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter1:inst17\|lpm_counter:lpm_counter_component\|cntr_7b7:auto_generated\|counter_cella3~COUT" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|reduce_nor~828 " "Info: Detected gated clock \"fspi:inst\|reduce_nor~828\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|reduce_nor~828" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|reduce_nor~817 " "Info: Detected gated clock \"fspi:inst\|reduce_nor~817\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|reduce_nor~817" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|reduce_nor~816 " "Info: Detected gated clock \"fspi:inst\|reduce_nor~816\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|reduce_nor~816" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|reduce_nor~97 " "Info: Detected gated clock \"fspi:inst\|reduce_nor~97\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|reduce_nor~97" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|reduce_nor~809 " "Info: Detected gated clock \"fspi:inst\|reduce_nor~809\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|reduce_nor~809" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fspi:inst\|count\[5\]~reg0 " "Info: Detected ripple clock \"fspi:inst\|count\[5\]~reg0\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 98 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|count\[5\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fspi:inst\|count\[6\]~reg0 " "Info: Detected ripple clock \"fspi:inst\|count\[6\]~reg0\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 98 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|count\[6\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fspi:inst\|count\[4\]~reg0 " "Info: Detected ripple clock \"fspi:inst\|count\[4\]~reg0\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 98 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|count\[4\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fspi:inst\|count\[3\]~reg0 " "Info: Detected ripple clock \"fspi:inst\|count\[3\]~reg0\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 98 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|count\[3\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fspi:inst\|count\[0\]~reg0 " "Info: Detected ripple clock \"fspi:inst\|count\[0\]~reg0\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 98 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|count\[0\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fspi:inst\|count\[1\]~reg0 " "Info: Detected ripple clock \"fspi:inst\|count\[1\]~reg0\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 98 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|count\[1\]~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fspi:inst\|count\[2\]~reg0 " "Info: Detected ripple clock \"fspi:inst\|count\[2\]~reg0\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 98 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|count\[2\]~reg0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|process1~0 " "Info: Detected gated clock \"fspi:inst\|process1~0\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|process1~0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|reduce_nor~3 " "Info: Detected gated clock \"fspi:inst\|reduce_nor~3\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|reduce_nor~3" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "syn_gen:inst2\|syn_out " "Info: Detected ripple clock \"syn_gen:inst2\|syn_out\" as buffer" {  } { { "syn_gen.vhd" "" { Text "D:/spi/send/spi backup/Fspi/syn_gen.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "syn_gen:inst2\|syn_out" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fspi:inst\|clkout " "Info: Detected gated clock \"fspi:inst\|clkout\" as buffer" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fspi:inst\|clkout" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll0:inst12\|altpll:altpll_component\|_clk0 register fspi:inst\|clkcount\[3\]~reg0 register fspi:inst\|enable~reg0 44.724 ns " "Info: Slack time is 44.724 ns for clock \"pll0:inst12\|altpll:altpll_component\|_clk0\" between source register \"fspi:inst\|clkcount\[3\]~reg0\" and destination register \"fspi:inst\|enable~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "189.54 MHz 5.276 ns " "Info: Fmax is 189.54 MHz (period= 5.276 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.739 ns + Largest register register " "Info: + Largest register to register requirement is 49.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 48.115 ns " "Info: + Latch edge is 48.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll0:inst12\|altpll:altpll_component\|_clk0 50.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"pll0:inst12\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll0:inst12\|altpll:altpll_component\|_clk0 50.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pll0:inst12\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll0:inst12\|altpll:altpll_component\|_clk0 destination 2.353 ns + Shortest register " "Info: + Shortest clock path from clock \"pll0:inst12\|altpll:altpll_component\|_clk0\" to destination register is 2.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll0:inst12\|altpll:altpll_component\|_clk0 1 CLK PLL_1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 33; CLK Node = 'pll0:inst12\|altpll:altpll_component\|_clk0'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "" { pll0:inst12|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.711 ns) 2.353 ns fspi:inst\|enable~reg0 2 REG LC_X28_Y8_N8 8 " "Info: 2: + IC(1.642 ns) + CELL(0.711 ns) = 2.353 ns; Loc. = LC_X28_Y8_N8; Fanout = 8; REG Node = 'fspi:inst\|enable~reg0'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 85 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 30.22 % " "Info: Total cell delay = 0.711 ns ( 30.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.78 % " "Info: Total interconnect delay = 1.642 ns ( 69.78 % )" {  } {  } 0}  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll0:inst12\|altpll:altpll_component\|_clk0 source 2.353 ns - Longest register " "Info: - Longest clock path from clock \"pll0:inst12\|altpll:altpll_component\|_clk0\" to source register is 2.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll0:inst12\|altpll:altpll_component\|_clk0 1 CLK PLL_1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 33; CLK Node = 'pll0:inst12\|altpll:altpll_component\|_clk0'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "" { pll0:inst12|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.711 ns) 2.353 ns fspi:inst\|clkcount\[3\]~reg0 2 REG LC_X29_Y9_N7 4 " "Info: 2: + IC(1.642 ns) + CELL(0.711 ns) = 2.353 ns; Loc. = LC_X29_Y9_N7; Fanout = 4; REG Node = 'fspi:inst\|clkcount\[3\]~reg0'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } "NODE_NAME" } "" } } { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 76 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 30.22 % " "Info: Total cell delay = 0.711 ns ( 30.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.78 % " "Info: Total interconnect delay = 1.642 ns ( 69.78 % )" {  } {  } 0}  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } } { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 76 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 85 -1 0 } }  } 0}  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } } { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.015 ns - Longest register register " "Info: - Longest register to register delay is 5.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fspi:inst\|clkcount\[3\]~reg0 1 REG LC_X29_Y9_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y9_N7; Fanout = 4; REG Node = 'fspi:inst\|clkcount\[3\]~reg0'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "" { fspi:inst|clkcount[3]~reg0 } "NODE_NAME" } "" } } { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 76 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.545 ns) + CELL(0.442 ns) 1.987 ns fspi:inst\|LessThan~333 2 COMB LC_X28_Y8_N5 1 " "Info: 2: + IC(1.545 ns) + CELL(0.442 ns) = 1.987 ns; Loc. = LC_X28_Y8_N5; Fanout = 1; COMB Node = 'fspi:inst\|LessThan~333'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "1.987 ns" { fspi:inst|clkcount[3]~reg0 fspi:inst|LessThan~333 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.442 ns) 2.826 ns fspi:inst\|LessThan~334 3 COMB LC_X28_Y8_N6 1 " "Info: 3: + IC(0.397 ns) + CELL(0.442 ns) = 2.826 ns; Loc. = LC_X28_Y8_N6; Fanout = 1; COMB Node = 'fspi:inst\|LessThan~334'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "0.839 ns" { fspi:inst|LessThan~333 fspi:inst|LessThan~334 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 3.844 ns fspi:inst\|LessThan~335 4 COMB LC_X28_Y8_N7 1 " "Info: 4: + IC(0.428 ns) + CELL(0.590 ns) = 3.844 ns; Loc. = LC_X28_Y8_N7; Fanout = 1; COMB Node = 'fspi:inst\|LessThan~335'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "1.018 ns" { fspi:inst|LessThan~334 fspi:inst|LessThan~335 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.738 ns) 5.015 ns fspi:inst\|enable~reg0 5 REG LC_X28_Y8_N8 8 " "Info: 5: + IC(0.433 ns) + CELL(0.738 ns) = 5.015 ns; Loc. = LC_X28_Y8_N8; Fanout = 8; REG Node = 'fspi:inst\|enable~reg0'" {  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "1.171 ns" { fspi:inst|LessThan~335 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 85 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns 44.11 % " "Info: Total cell delay = 2.212 ns ( 44.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.803 ns 55.89 % " "Info: Total interconnect delay = 2.803 ns ( 55.89 % )" {  } {  } 0}  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "5.015 ns" { fspi:inst|clkcount[3]~reg0 fspi:inst|LessThan~333 fspi:inst|LessThan~334 fspi:inst|LessThan~335 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.015 ns" { fspi:inst|clkcount[3]~reg0 fspi:inst|LessThan~333 fspi:inst|LessThan~334 fspi:inst|LessThan~335 fspi:inst|enable~reg0 } { 0.000ns 1.545ns 0.397ns 0.428ns 0.433ns } { 0.000ns 0.442ns 0.442ns 0.590ns 0.738ns } } }  } 0}  } { { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|enable~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } } { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { pll0:inst12|altpll:altpll_component|_clk0 fspi:inst|clkcount[3]~reg0 } { 0.000ns 1.642ns } { 0.000ns 0.711ns } } } { "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" "" { Report "D:/spi/send/spi backup/Fspi/db/Fspi_cmp.qrpt" Compiler "Fspi" "UNKNOWN" "V1" "D:/spi/send/spi backup/Fspi/db/Fspi.quartus_db" { Floorplan "D:/spi/send/spi backup/Fspi/" "" "5.015 ns" { fspi:inst|clkcount[3]~reg0 fspi:inst|LessThan~333 fspi:inst|LessThan~334 fspi:inst|LessThan~335 fspi:inst|enable~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.015 ns" { fspi:inst|clkcount[3]~reg0 fspi:inst|LessThan~333 fspi:inst|LessThan~334 fspi:inst|LessThan~335 fspi:inst|enable~reg0 } { 0.000ns 1.545ns 0.397ns 0.428ns 0.433ns } { 0.000ns 0.442ns 0.442ns 0.590ns 0.738ns } } }  } 0}