📄 dcfifo_miu.tdf
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--dcfifo ADD_RAM_OUTPUT_REGISTER="ON" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=64 LPM_WIDTHU=8 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" data q rdclk rdempty rdreq wrclk wrfull wrreq
--VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
-- Copyright (C) 1988-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION a_gray2bin_p4b (gray[7..0])
RETURNS ( bin[7..0]);
FUNCTION a_graycounter_i06 (aclr, clk_en, clock)
RETURNS ( q[7..0]);
FUNCTION a_graycounter_j06 (aclr, clk_en, clock)
RETURNS ( q[7..0]);
FUNCTION altsyncram_p3v (address_a[7..0], address_b[7..0], clock0, clock1, clocken1, data_a[63..0], wren_a)
RETURNS ( q_b[63..0]);
FUNCTION alt_synch_pipe_2a3 (clock, clrn, d[7..0])
RETURNS ( q[7..0]);
FUNCTION alt_synch_pipe_3a3 (clock, clrn, d[7..0])
RETURNS ( q[7..0]);
FUNCTION add_sub_fub (dataa[7..0], datab[7..0])
RETURNS ( result[7..0]);
FUNCTION cntr_uu7 (aclr, clk_en, clock)
RETURNS ( cout, q[7..0]);
PARAMETERS
(
lpm_widthu = 1
);
FUNCTION scfifo (aclr, clock, data[lpm_width-1..0], rdreq, sclr, wrreq)
WITH ( ADD_RAM_OUTPUT_REGISTER, ALLOW_RWCYCLE_WHEN_FULL, ALMOST_EMPTY_VALUE, ALMOST_FULL_VALUE, LPM_NUMWORDS, LPM_SHOWAHEAD, lpm_width, lpm_widthu, OVERFLOW_CHECKING, UNDERFLOW_CHECKING, USE_EAB)
RETURNS ( almost_empty, almost_full, empty, full, q[lpm_width-1..0], usedw[lpm_widthu-1..0]);
--synthesis_resources = lut 176 M4K 4 scfifo 1
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from ""read_counter_for_write|power_modified_counter_values"" -to ""write_sync_registers|dffpipe14|dffe15a"" }CUT=ON;{ -from ""delayed_wrptr_g"" -to ""read_sync_registers|dffpipe10|dffe11a"" }CUT=ON";
SUBDESIGN dcfifo_miu
(
data[63..0] : input;
q[63..0] : output;
rdclk : input;
rdempty : output;
rdfull : output;
rdreq : input;
rdusedw[7..0] : output;
wrclk : input;
wrempty : output;
wrfull : output;
wrreq : input;
wrusedw[7..0] : output;
)
VARIABLE
read_side_gray_converter : a_gray2bin_p4b;
write_side_gray_converter : a_gray2bin_p4b;
rdptr_g : a_graycounter_i06;
read_counter_for_write : a_graycounter_j06;
wrptr_g : a_graycounter_i06;
fifo_ram : altsyncram_p3v;
delayed_wrptr_g[7..0] : dffe;
dffe2a[7..0] : dffe;
dffe3a[7..0] : dffe;
dffe4a[7..0] : dffe;
dffe6a[7..0] : dffe;
dffe7a[7..0] : dffe;
dffe8a[7..0] : dffe;
fifo_wreq_pipe[1..0] : dffe;
lwrreq : dffe;
rdfull_delay : dffe;
wrempty_delay : dffe;
wrfull_delay : dffe;
read_sync_registers : alt_synch_pipe_2a3;
write_sync_registers : alt_synch_pipe_3a3;
rdusedw_subtractor : add_sub_fub;
wrusedw_subtractor : add_sub_fub;
address_comparer_aeb_int : WIRE;
address_comparer_aeb : WIRE;
address_comparer_dataa[7..0] : WIRE;
address_comparer_datab[7..0] : WIRE;
rdfull_compare_aeb_int : WIRE;
rdfull_compare_agb_int : WIRE;
rdfull_compare_ageb : WIRE;
rdfull_compare_dataa[7..0] : WIRE;
rdfull_compare_datab[7..0] : WIRE;
wrempty_comparison_aeb_int : WIRE;
wrempty_comparison_aeb : WIRE;
wrempty_comparison_dataa[7..0] : WIRE;
wrempty_comparison_datab[7..0] : WIRE;
wrfull_comparison_aeb_int : WIRE;
wrfull_comparison_agb_int : WIRE;
wrfull_comparison_ageb : WIRE;
wrfull_comparison_dataa[7..0] : WIRE;
wrfull_comparison_datab[7..0] : WIRE;
rdptr_b : cntr_uu7;
wrptr_b : cntr_uu7;
output_channel : scfifo
WITH (
ADD_RAM_OUTPUT_REGISTER = "ON",
LPM_NUMWORDS = 3,
LPM_SHOWAHEAD = "OFF",
lpm_width = 64,
lpm_widthu = 2,
OVERFLOW_CHECKING = "ON",
UNDERFLOW_CHECKING = "ON",
USE_EAB = "OFF"
);
aclr : NODE;
delayed_read_counter_after_gray_conversion[7..0] : WIRE;
delayed_write_counter_after_gray_conversion[7..0] : WIRE;
fifo_wreq_out : WIRE;
pre_rdempty : WIRE;
pre_wrfull : WIRE;
ramread_address[7..0] : WIRE;
rdusedw_delaypipe_out[7..0] : WIRE;
read_count_after_gray_conversion[7..0] : WIRE;
read_count_for_write_side[7..0] : WIRE;
read_count_to_write_side[7..0] : WIRE;
stall_pipeline : WIRE;
valid_rreq : WIRE;
valid_wrreq : WIRE;
write_count_after_gray_conversion[7..0] : WIRE;
write_count_for_read_side[7..0] : WIRE;
write_count_to_read_side[7..0] : WIRE;
wrusedw_delaypipe_out[7..0] : WIRE;
BEGIN
read_side_gray_converter.gray[] = write_count_for_read_side[];
write_side_gray_converter.gray[] = read_count_for_write_side[];
rdptr_g.aclr = aclr;
rdptr_g.clk_en = ((! stall_pipeline) & (! address_comparer_aeb));
rdptr_g.clock = rdclk;
read_counter_for_write.aclr = aclr;
read_counter_for_write.clk_en = valid_rreq;
read_counter_for_write.clock = rdclk;
wrptr_g.aclr = aclr;
wrptr_g.clk_en = valid_wrreq;
wrptr_g.clock = wrclk;
fifo_ram.address_a[] = wrptr_g.q[];
fifo_ram.address_b[] = ramread_address[];
fifo_ram.clock0 = wrclk;
fifo_ram.clock1 = rdclk;
fifo_ram.clocken1 = (! stall_pipeline);
fifo_ram.data_a[] = data[];
fifo_ram.wren_a = valid_wrreq;
delayed_wrptr_g[].CLK = wrclk;
delayed_wrptr_g[].CLRN = (! aclr);
delayed_wrptr_g[].D = wrptr_g.q[];
dffe2a[].CLK = wrclk;
dffe2a[].CLRN = (! aclr);
dffe2a[].D = read_count_after_gray_conversion[];
dffe3a[].CLK = wrclk;
dffe3a[].CLRN = (! aclr);
dffe3a[].D = wrusedw_subtractor.result[];
dffe4a[].CLK = wrclk;
dffe4a[].CLRN = (! aclr);
dffe4a[].D = wrusedw_subtractor.result[];
dffe6a[].CLK = rdclk;
dffe6a[].CLRN = (! aclr);
dffe6a[].D = write_count_after_gray_conversion[];
dffe7a[].CLK = rdclk;
dffe7a[].CLRN = (! aclr);
dffe7a[].D = rdusedw_subtractor.result[];
dffe8a[].CLK = rdclk;
dffe8a[].CLRN = (! aclr);
dffe8a[].D = rdusedw_subtractor.result[];
fifo_wreq_pipe[].CLK = rdclk;
fifo_wreq_pipe[].CLRN = (! aclr);
fifo_wreq_pipe[0].D = ((stall_pipeline & fifo_wreq_pipe[0].Q) # ((! stall_pipeline) & (! address_comparer_aeb)));
fifo_wreq_pipe[1].D = ((fifo_wreq_pipe[0].Q & (! stall_pipeline)) # (fifo_wreq_pipe[1].Q & stall_pipeline));
lwrreq.CLK = wrclk;
lwrreq.CLRN = (! aclr);
lwrreq.D = wrreq;
rdfull_delay.CLK = rdclk;
rdfull_delay.CLRN = (! aclr);
rdfull_delay.D = rdfull_compare_ageb;
wrempty_delay.CLK = wrclk;
wrempty_delay.CLRN = (! aclr);
wrempty_delay.D = (! (((! wrreq) & (! lwrreq.Q)) & wrempty_comparison_aeb));
wrfull_delay.CLK = wrclk;
wrfull_delay.CLRN = (! aclr);
wrfull_delay.D = wrfull_comparison_ageb;
read_sync_registers.clock = rdclk;
read_sync_registers.clrn = (! aclr);
read_sync_registers.d[] = write_count_to_read_side[];
write_sync_registers.clock = wrclk;
write_sync_registers.clrn = (! aclr);
write_sync_registers.d[] = read_count_to_write_side[];
rdusedw_subtractor.dataa[] = delayed_write_counter_after_gray_conversion[];
rdusedw_subtractor.datab[] = rdptr_b.q[];
wrusedw_subtractor.dataa[] = wrptr_b.q[];
wrusedw_subtractor.datab[] = delayed_read_counter_after_gray_conversion[];
IF (address_comparer_dataa[] == address_comparer_datab[]) THEN
address_comparer_aeb_int = VCC;
ELSE
address_comparer_aeb_int = GND;
END IF;
address_comparer_aeb = address_comparer_aeb_int;
address_comparer_dataa[] = rdptr_g.q[];
address_comparer_datab[] = write_count_for_read_side[];
IF (rdfull_compare_dataa[] == rdfull_compare_datab[]) THEN
rdfull_compare_aeb_int = VCC;
rdfull_compare_agb_int = GND;
ELSIF (rdfull_compare_dataa[] > rdfull_compare_datab[]) THEN
rdfull_compare_agb_int = VCC;
rdfull_compare_aeb_int = GND;
ELSE
rdfull_compare_aeb_int = GND;
rdfull_compare_agb_int = GND;
END IF;
rdfull_compare_ageb = rdfull_compare_agb_int # rdfull_compare_aeb_int;
rdfull_compare_dataa[] = rdusedw_delaypipe_out[];
rdfull_compare_datab[] = B"11111101";
IF (wrempty_comparison_dataa[] == wrempty_comparison_datab[]) THEN
wrempty_comparison_aeb_int = VCC;
ELSE
wrempty_comparison_aeb_int = GND;
END IF;
wrempty_comparison_aeb = wrempty_comparison_aeb_int;
wrempty_comparison_dataa[] = wrusedw_delaypipe_out[];
wrempty_comparison_datab[] = B"00000000";
IF (wrfull_comparison_dataa[] == wrfull_comparison_datab[]) THEN
wrfull_comparison_aeb_int = VCC;
wrfull_comparison_agb_int = GND;
ELSIF (wrfull_comparison_dataa[] > wrfull_comparison_datab[]) THEN
wrfull_comparison_agb_int = VCC;
wrfull_comparison_aeb_int = GND;
ELSE
wrfull_comparison_aeb_int = GND;
wrfull_comparison_agb_int = GND;
END IF;
wrfull_comparison_ageb = wrfull_comparison_agb_int # wrfull_comparison_aeb_int;
wrfull_comparison_dataa[] = wrusedw_delaypipe_out[];
wrfull_comparison_datab[] = B"11111101";
rdptr_b.aclr = aclr;
rdptr_b.clk_en = valid_rreq;
rdptr_b.clock = rdclk;
wrptr_b.aclr = aclr;
wrptr_b.clk_en = valid_wrreq;
wrptr_b.clock = wrclk;
output_channel.aclr = aclr;
output_channel.clock = rdclk;
output_channel.data[] = fifo_ram.q_b[];
output_channel.rdreq = rdreq;
output_channel.wrreq = fifo_wreq_out;
aclr = GND;
delayed_read_counter_after_gray_conversion[] = dffe2a[].Q;
delayed_write_counter_after_gray_conversion[] = dffe6a[].Q;
fifo_wreq_out = fifo_wreq_pipe[1].Q;
pre_rdempty = output_channel.empty;
pre_wrfull = wrfull_delay.Q;
q[] = output_channel.q[];
ramread_address[] = rdptr_g.q[];
rdempty = pre_rdempty;
rdfull = rdfull_delay.Q;
rdusedw[] = dffe8a[].Q;
rdusedw_delaypipe_out[] = dffe7a[].Q;
read_count_after_gray_conversion[] = write_side_gray_converter.bin[];
read_count_for_write_side[] = write_sync_registers.q[];
read_count_to_write_side[] = read_counter_for_write.q[];
stall_pipeline = (output_channel.full & fifo_wreq_pipe[1].Q);
valid_rreq = (rdreq & (! pre_rdempty));
valid_wrreq = ((! pre_wrfull) & wrreq);
wrempty = (! wrempty_delay.Q);
wrfull = pre_wrfull;
write_count_after_gray_conversion[] = read_side_gray_converter.bin[];
write_count_for_read_side[] = read_sync_registers.q[];
write_count_to_read_side[] = delayed_wrptr_g[].Q;
wrusedw[] = dffe4a[].Q;
wrusedw_delaypipe_out[] = dffe3a[].Q;
END;
--VALID FILE
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