send_top.vhd

很多仪器都输出同步时钟

library IEEE;
use IEEE.std_logic_1164.all;
use WORK.SEND_PACKAGE.all;

entity send_top is

  generic(
     
	DATA_BIT : integer := 64;                  -- 数据位个数
	TOTAL_BIT : integer := 66                -- 总数据个数
 );
  port(	  
       clk : in STD_LOGIC;               -- 时钟信号
       rdclk:out std_logic;              -- 读fifo的时钟
       rdempty:in std_logic;             --读空标志
       rdreq:out std_logic;
  --     send : in STD_LOGIC;              -- 发送控制信号
       send_bus : in STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);-- 数据发送总线
  --     send_over : out STD_LOGIC;        -- 发送完成信号
       RxD :in std_logic;
  --     dout :out std_logic_vector(5 downto 0);
       TxD : out STD_LOGIC );            -- RS-232数据发送端口
end send_top;

architecture send_top of send_top is

-- 计数器组件声明
component counter
  generic(
       MAX_COUNT : INTEGER := 66
  );
  port (
       ce : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       overflow : out STD_LOGIC
  );
end component;
---奇偶校验模块
component parity_verifier is
	-- 类属参数
	generic (
	DATA_LENGTH : integer := 64;
	PARITY_RULE : PARITY := ODD );
	-- 端口
	port (
	source : in std_logic_vector(DATA_LENGTH-1 downto 0);
	parity : out std_logic );
end component;

-- 移位寄存器
component shift_register
  generic(
       TOTAL_BIT : INTEGER := 67
  );
  port (
       clk : in STD_LOGIC;
       din : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       dout : out STD_LOGIC
  );
end component;
component detector1 is
	port (
	clk : in std_logic;
	reset_n : in std_logic;
	RxD : in std_logic;          --输入信号
	new_data : out std_logic );  --指示信号，当监测到新的数据传输时置高
end component;

-- 二选一选择器
component switch
  port (
       din1 : in STD_LOGIC;
       din2 : in STD_LOGIC;
       sel : in STD_LOGIC;
       dout : out STD_LOGIC
  );
end component;

-- UART内核
component send_core is
	generic (
	
	DATA_BIT : integer := 64;-- 数据位个数
	TOTAL_BIT : integer := 66;-- 总数据个数
	PARITY_RULE:PARITY := ODD 
     );
	port (
	-- 时钟信号
	clk : in std_logic;
	rdclk:out std_logic;              -- 读fifo的时钟
    rdempty:in std_logic;             --读空标志
    rdreq:out std_logic;
	-- 复位、使能子模块的信号
	reset_parts : out std_logic;
	reset_dt:out std_logic;
	ce_parts : out std_logic;
	new_data:in std_logic;
	-- 和移位寄存器的接口信号
	RxD:in std_logic;
	send_si : out std_logic;
    --计数器计数到达上阈的指示信号
	overflow : in std_logic;
 --   dout :out std_logic_vector(5 downto 0);
	parity:in std_logic;
	-- 输出选择信号
	sel_out : out std_logic;
	-- 提供给CPU的接口信号
	--send : in std_logic;
	send_bus : in std_logic_vector(DATA_BIT-1 downto 0)
--	send_bus_2: out std_logic_vector(63 downto 0);
--	send_over : out std_logic
	);
end component;
----     常数     -----
constant VCC_CONSTANT   : STD_LOGIC := '1';
---- 内部信号声明 ----
signal ce_parts : STD_LOGIC;
signal clk_inv : STD_LOGIC;
signal counter_clk : STD_LOGIC;
signal overflow : STD_LOGIC;
signal sr_out:STD_LOGIC;
signal reset_parts : STD_LOGIC;
signal sel_clk : STD_LOGIC;
signal sel_out : STD_LOGIC;
signal send_si : STD_LOGIC;
signal VCC : STD_LOGIC;
signal parity:std_logic;
signal new_data:std_logic;
signal reset_dt:std_logic;
--signal send_bus_2:std_logic_vector(63 downto 0);

begin

	-- 信号连接
	VCC <= VCC_CONSTANT;   

	-- UART内核实例
	U_Core : send_core
	  port map(
	       ce_parts => ce_parts,
	       clk => clk,
	       overflow => overflow,
	       reset_parts => reset_parts,
	       reset_dt => reset_dt,
	       rdclk => rdclk,
	       rdempty => rdempty,
	       rdreq => rdreq,
	       sel_out => sel_out,
	       parity => parity,
	       new_data=> new_data,
	--       send => send,
	       RxD => RxD,
	--       dout => dout ,
	       send_bus => send_bus,
--	       send_bus_2 => send_bus_2,
	--       send_over => send_over,
	       send_si => send_si
	  );
	-- 计数器实例
	U_Counter : counter
	  port map(
	       ce => ce_parts,
	       clk => clk,
	       overflow => overflow,
	       reset_n => reset_parts
	  );
	-- 移位寄存器实例
	U_SR : shift_register
	  port map(
	       clk => clk,
	       din => send_si,
	       dout => sr_out,
	       reset_n => reset_parts
	  );
	-- 输出选择器实例
	U_TXDSwitch : switch
	  port map(
	       din1 => VCC,
	       din2 => sr_out,
	       dout => TxD,
	       sel => sel_out
	  );
	U_PV:parity_verifier
	  port map(
	       source => send_bus,
	       parity => parity
	);
	U_detector:detector1
	  port map(
	       clk => clk,
	       reset_n => reset_dt,
	       RxD => RxD,
	       new_data => new_data
	 );  
	
end send_top;