recv_core.vhd

很多仪器都输出同步时钟

-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.RECV_PACKAGE.all;

entity recv_core is
	generic (
	
	DATA_BIT : integer := 64;-- 数据位个数
	TOTAL_BIT : integer := 66;-- 总数据个数
    PARITY_RULE:PARITY:=ODD
    );
	port (
	-- 时钟和复位信号
	clk : in std_logic;
	-- 和信号监测器的接口信号
	new_data : in std_logic;
	reset_dt : out std_logic;
	-- 复位、使能子模块的信号
	reset_parts : out std_logic;
	reset_shift:out std_logic;
	ce_parts : out std_logic;
	parity:in std_logic;
	sel_TxD:out std_logic;
	-- 和移位寄存器的接口信号
	regs : in std_logic_vector(68 downto 0);
	-- 计数器时钟选择信号和计数器计数到达上阈的指示信号
	overflow : in std_logic;
	-- 提供给CPU的接口信号
	wrfull: in std_logic;
	wrreq : out std_logic;
	wrclk : out std_logic;
	TxD  : out std_logic;
	pv_in:out std_logic_vector(DATA_BIT-1 downto 0);
	recv_bus : out std_logic_vector(DATA_BIT-1 downto 0)
	 );
	
end recv_core;


architecture recv_core of recv_core is

-- 内部信号
signal state : UART_STATE := UART_IDLE;
signal reg:std_logic;
signal reg4:std_logic_vector(5 downto 0);
signal count1:integer;
signal error :std_logic;
signal full:std_logic := '0';

begin
    wrclk <= clk;
	-- 主过程
	main: process(clk)
	begin
        if rising_edge(clk) then
		      case state is
		    	when UART_IDLE =>      -- 空闲状态
		        if wrfull='1' then
		              full <= wrfull;
					  count1 <= 0;
		              state <= SEND_BACK;
		        else 		            
		     		if new_data = '1' then -- 当信号监测器监测到数据时，new_data变为'1'
		    			reset_parts <= '0';-- 复位子模块
		   	    		ce_parts <= '0';   -- 子模块使能无效
		   	    		reset_shift <= '1';
		                sel_TxD <= '0';
		                error <= '0';
		                wrreq <= '0';
		   	    		state <= UART_RECV;-- 改变状态为接收
		   	    	else	
		    	        sel_TxD <= '0';
                        error <= '0';
		    	        wrreq <= '0';
		    	        reset_dt <= '1';   -- 停止对信号监测器的复位
		    		end if;
               end if; 
				-------- 数据接收状态--------
				-- 接收状态
				when UART_RECV =>
				
				if overflow = '1' then     -- 如果overflow变为"1"，表示接收完成
					reg <= regs(65);
					recv_bus <= regs(DATA_BIT downto 1);-- 总线数据输出
					pv_in <= regs(DATA_BIT downto 1);
					state <= UART_END_RECV;-- 改变状态为接收完成
				else
					reset_parts <= '1';    -- 子模块复位信号无效
					ce_parts <= '1';       -- 子模块使能信号有效
					reset_shift <= '1';
				end if;
				
				-- 接收完成状态
				when UART_END_RECV =>
				
				if not( reg = parity) then
				    error <= '1';
				else
					wrreq <= '1';		   -- 输出接收指示信号  
				end if;
				ce_parts <= '0';              -- 子模块使能信号无效
				count1 <= 0;
				state <= SEND_BACK;           -- 改变状态为空闲
				
				when SEND_BACK =>
				    if not(count1 = 6) then
		        	   sel_TxD <= '1';
                       TxD <= reg4(5- count1);
                       count1 <= count1 +1;
                     else
                        sel_TxD <= '0';
                        full <= '0';
 	        			reset_dt <= '0';              -- 复位信号监测器
                        state <= UART_IDLE;
                    end if;
                   wrreq <= '0';

				when others =>                -- 如果产生未知状态，输出错误信息
				error <= '1';
				state <= UART_IDLE;           -- 恢复到空闲状态
			  end case;
		end if;
	end process;	
  ---------------------------   
    process (error, full)
    begin 
          if rising_edge(clk) then
              if error = '1' and full ='0' then      --发错
                 reg4 <= "000001";
              elsif error = '0' and full = '1' then   --fifo满
                 reg4 <= "000010";
              else                        --正确
                 reg4 <= "000000";
              end if;
           end if;
    end process;
 
end recv_core;