testsend.vhd

来自「很多仪器都输出同步时钟」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_unsigned.all;
entity testsend is
port(data:out std_logic_vector(63 downto 0));
end testsend;
architecture rtl of testsend is 
begin

data<="1111111100000000111111110000000011111111000000001111111100000000";

end rtl;