fifo_inst.vhd

来自「很多仪器都输出同步时钟」· VHDL 代码 · 共 11 行

fifo_inst : fifo PORT MAP (
		data	 => data_sig,
		wrreq	 => wrreq_sig,
		rdreq	 => rdreq_sig,
		rdclk	 => rdclk_sig,
		wrclk	 => wrclk_sig,
		q	 => q_sig,
		rdempty	 => rdempty_sig,
		wrfull	 => wrfull_sig
	);