fspi.vhd

很多仪器都输出同步时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_unsigned.all;
entity fspi is
port(spiclk,spisimo,spiste,empty,clk:in std_logic;
     spisomi,spiclkout:out std_logic;
     dspds,dspis,dspps,dsprw,dsprd,dspwe,dspstrb,dspvisoe:in std_logic;
     d,a:in std_logic_vector(15 downto 0);
     ready,rsdsp:out std_logic;
     re:out std_logic;
     fiforead,clkout:buffer std_logic;
     count:buffer std_logic_vector(6 downto 0); 
     datain:out std_logic_vector(63 downto 0);
     dataout:in std_logic_vector(0 to 63);
     enable,clk1:buffer std_logic;
     wrreq,wrclk:out std_logic;
     wrfull:in std_logic;
     clkcount:buffer std_logic_vector(31 downto 0);
     testdata:buffer std_logic_vector(0 to 63)); 
end fspi;

architecture rtl of fspi is 

signal din:std_logic_vector(95 downto 0);
signal dout:std_logic_vector(0 to 95);
signal clkcount1:std_logic_vector(31 downto 0);
begin
ready<='1';
rsdsp<='1';
spiclkout<=spiclk;
process(spiclk)  --spi接收程序（实现spi串行数据输入，有效数据包并行输出）
begin
	if(spiclk'event and spiclk='1')
	  then din(0)<=spisimo;--spi输入
	  for i in 0 to 94 loop
	       din(i+1)<=din(i);
	  end loop;  
       if(din(95 downto 80)="1010101010101010")--数据包头检测输出
        then
	   if(din(15 downto 0)=din(31 downto 16)+din(47 downto 32)+din(63 downto 48)+din(79 downto 64))--数据包效验
	       then datain<=din(79 downto 16);
	           re<='1';
	   end if;
	   end if;
	 end if;
end process;


process(clkout)
begin
  if(count=95)
     then fiforead<='1';
  end if;    
  if((count=0)and(fiforead='1'))
    then clkout<='1';
  end if;
  if(clkout'event and clkout='1')
    then 
     if(empty='0') 
       then dout(0 to 15)<="1010101010101010";
            dout(16 to 79)<=dataout;
            dout(80 to 95)<=dataout(0 to 15)+dataout(16 to 31)+dataout(32 to 47)+dataout(48 to 63);
  else
     dout<="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
 end if; 
 end if;
 if(count=1)
    then 
       fiforead<='0';
         clkout<='0';
  end if;
end process;

process(clk)
begin
if(spiclk='0') then
   clkcount<=(others=>'0'); 
elsif(clk'event and clk='1') then
   clkcount<=clkcount+'1';
end if;
end process;

process(clk)
begin    
if(clk'event and clk='1')
    then if(clkcount>=15000)
          then enable<='0';
  --       end if;
      elsif(spiclk='0')
          then enable<='1';
         end if;        
end if;
end process;


process(spiclk)
begin
if(enable='0') then
   count<=(others=>'0');
elsif(spiclk'event and spiclk='0') then 
     count<=count+'1';
end if;
end process;


process(count)
begin
for m in 0 to 95 loop
       if(count=m)then spisomi<=dout(m);
           end if;
end loop;
end process;





process(clkout)
begin
wrreq<='1';
if(clkout'event and clkout='1')
then if(wrfull='0') then   
   testdata<="1000000000000000100000000000000010000000000000001000000000000000";
end if;
end if;
end process;
end rtl;