spitest.vhd

很多仪器都输出同步时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_unsigned.all;
entity spitest is
port(spiclk,spisimo,spiste,empty,clk:in std_logic;
     spisomi,spiclkout,fiforead,clkout:out std_logic;
     dspds,dspis,dspps,dsprw,dsprd,dspwe,dspstrb,dspvisoe:in std_logic;
     d,a:in std_logic_vector(15 downto 0);
     ready,rsdsp:out std_logic;
     re:out std_logic;
     count:buffer std_logic_vector(6 downto 0); 
     datain:out std_logic_vector(63 downto 0));
end spitest;

architecture rtl of spitest is 
signal k:std_logic;
signal din:std_logic_vector(95 downto 0);
begin
ready<='1';
rsdsp<='1';
spiclkout<=spiclk;
clkout<=clk;
process(spiclk)  --spi接收程序（实现spi串行数据输入，有效数据包并行输出）
begin
	if(spiclk'event and spiclk='1')
	  then din(0)<=spisimo;--spi输入
	  for i in 0 to 94 loop
	       din(i+1)<=din(i);
	  end loop;  
	   if(k='1')then count<=count+'1'; --96位数据包计数器
	     end if;  
	   if(count=95)then count<="0000000";
	     end if; 
	   if(din(95 downto 80)="1010101010101010")--有效数据包检测输出
	      then k<='1';
	   if(din(15 downto 0)=din(31 downto 16)+din(47 downto 32)+din(63 downto 48)+din(79 downto 64))
	       then datain<=din(79 downto 16);
	           re<='1';
	   end if;
	   end if;
	 end if;
end process;


process(count)
begin

end rtl;