dm642_syn.tan.rpt

一个用vHDL语言编的同步程序

; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[1]  ; syn_count[6]   ; clk        ; clk      ; None                        ; None                      ; 3.327 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[5]  ; syn_count[9]   ; clk        ; clk      ; None                        ; None                      ; 3.324 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[8]  ; syn_count[15]  ; clk        ; clk      ; None                        ; None                      ; 3.311 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[0]  ; syn_count[12]  ; clk        ; clk      ; None                        ; None                      ; 3.309 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[13] ; syn_count[18]  ; clk        ; clk      ; None                        ; None                      ; 3.307 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[8]  ; syn_count[14]  ; clk        ; clk      ; None                        ; None                      ; 3.301 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[13] ; syn_count[20]  ; clk        ; clk      ; None                        ; None                      ; 3.301 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[12] ; syn_count[14]  ; clk        ; clk      ; None                        ; None                      ; 3.299 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[12] ; syn_count[13]  ; clk        ; clk      ; None                        ; None                      ; 3.294 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[4]  ; syn_ir~reg0    ; clk        ; clk      ; None                        ; None                      ; 3.290 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[11] ; syn_count[15]  ; clk        ; clk      ; None                        ; None                      ; 3.280 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[2]  ; syn_count[19]  ; clk        ; clk      ; None                        ; None                      ; 3.280 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[5]  ; syn_count[6]   ; clk        ; clk      ; None                        ; None                      ; 3.278 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[8]  ; syn_count[12]  ; clk        ; clk      ; None                        ; None                      ; 3.271 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[17] ; syn_count[19]  ; clk        ; clk      ; None                        ; None                      ; 3.270 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[10] ; syn_count[13]  ; clk        ; clk      ; None                        ; None                      ; 3.267 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[13] ; syn_count[11]  ; clk        ; clk      ; None                        ; None                      ; 3.263 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[13] ; syn_count[6]   ; clk        ; clk      ; None                        ; None                      ; 3.258 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[13] ; syn_count[10]  ; clk        ; clk      ; None                        ; None                      ; 3.258 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; syn_count[13] ; syn_count[8]   ; clk        ; clk      ; None                        ; None                      ; 3.258 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;               ;                ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From           ; To        ; From Clock ;
+-------+--------------+------------+----------------+-----------+------------+
; N/A   ; None         ; 7.696 ns   ; syn_dm642~reg0 ; syn_dm642 ; clk        ;
; N/A   ; None         ; 7.010 ns   ; syn_ir~reg0    ; syn_ir    ; clk        ;
+-------+--------------+------------+----------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 09 20:18:24 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DM642_syn -c DM642_syn --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 209.95 MHz between source register "syn_count[7]" and destination register "syn_count[17]" (period= 4.763 ns)
    Info: + Longest register to register delay is 4.502 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y16_N9; Fanout = 5; REG Node = 'syn_count[7]'
        Info: 2: + IC(1.149 ns) + CELL(0.423 ns) = 1.572 ns; Loc. = LC_X11_Y16_N1; Fanout = 2; COMB Node = 'Add0~354'
        Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.650 ns; Loc. = LC_X11_Y16_N2; Fanout = 2; COMB Node = 'Add0~350'
        Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.728 ns; Loc. = LC_X11_Y16_N3; Fanout = 2; COMB Node = 'Add0~352'
        Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.906 ns; Loc. = LC_X11_Y16_N4; Fanout = 6; COMB Node = 'Add0~332'
        Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 2.114 ns; Loc. = LC_X11_Y16_N9; Fanout = 6; COMB Node = 'Add0~334'
        Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 2.793 ns; Loc. = LC_X11_Y15_N1; Fanout = 1; COMB Node = 'Add0~369'
        Info: 8: + IC(1.231 ns) + CELL(0.478 ns) = 4.502 ns; Loc. = LC_X12_Y16_N8; Fanout = 5; REG Node = 'syn_count[17]'
        Info: Total cell delay = 2.122 ns ( 47.13 % )
        Info: Total interconnect delay = 2.380 ns ( 52.87 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y16_N8; Fanout = 5; REG Node = 'syn_count[17]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "clk" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y16_N9; Fanout = 5; REG Node = 'syn_count[7]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "syn_dm642" through register "syn_dm642~reg0" is 7.696 ns
    Info: + Longest clock path from clock "clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y16_N4; Fanout = 1; REG Node = 'syn_dm642~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.518 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y16_N4; Fanout = 1; REG Node = 'syn_dm642~reg0'
        Info: 2: + IC(2.394 ns) + CELL(2.124 ns) = 4.518 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'syn_dm642'
        Info: Total cell delay = 2.124 ns ( 47.01 % )
        Info: Total interconnect delay = 2.394 ns ( 52.99 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 137 megabytes of memory during processing
    Info: Processing ended: Thu Apr 09 20:18:24 2009
    Info: Elapsed time: 00:00:00