dm642_syn.tan.qmsg

来自「一个用vHDL语言编的同步程序」· QMSG 代码 · 共 8 行 · 第 1/2 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register syn_count\[7\] register syn_count\[17\] 209.95 MHz 4.763 ns Internal " "Info: Clock \"clk\" has Internal fmax of 209.95 MHz between source register \"syn_count\[7\]\" and destination register \"syn_count\[17\]\" (period= 4.763 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.502 ns + Longest register register " "Info: + Longest register to register delay is 4.502 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns syn_count\[7\] 1 REG LC_X13_Y16_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y16_N9; Fanout = 5; REG Node = 'syn_count\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { syn_count[7] } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.149 ns) + CELL(0.423 ns) 1.572 ns Add0~354 2 COMB LC_X11_Y16_N1 2 " "Info: 2: + IC(1.149 ns) + CELL(0.423 ns) = 1.572 ns; Loc. = LC_X11_Y16_N1; Fanout = 2; COMB Node = 'Add0~354'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { syn_count[7] Add0~354 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.650 ns Add0~350 3 COMB LC_X11_Y16_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.650 ns; Loc. = LC_X11_Y16_N2; Fanout = 2; COMB Node = 'Add0~350'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { Add0~354 Add0~350 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.728 ns Add0~352 4 COMB LC_X11_Y16_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.728 ns; Loc. = LC_X11_Y16_N3; Fanout = 2; COMB Node = 'Add0~352'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { Add0~350 Add0~352 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.906 ns Add0~332 5 COMB LC_X11_Y16_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.906 ns; Loc. = LC_X11_Y16_N4; Fanout = 6; COMB Node = 'Add0~332'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Add0~352 Add0~332 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.114 ns Add0~334 6 COMB LC_X11_Y16_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 2.114 ns; Loc. = LC_X11_Y16_N9; Fanout = 6; COMB Node = 'Add0~334'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~332 Add0~334 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.793 ns Add0~369 7 COMB LC_X11_Y15_N1 1 " "Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 2.793 ns; Loc. = LC_X11_Y15_N1; Fanout = 1; COMB Node = 'Add0~369'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { Add0~334 Add0~369 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.478 ns) 4.502 ns syn_count\[17\] 8 REG LC_X12_Y16_N8 5 " "Info: 8: + IC(1.231 ns) + CELL(0.478 ns) = 4.502 ns; Loc. = LC_X12_Y16_N8; Fanout = 5; REG Node = 'syn_count\[17\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { Add0~369 syn_count[17] } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.122 ns ( 47.13 % ) " "Info: Total cell delay = 2.122 ns ( 47.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.380 ns ( 52.87 % ) " "Info: Total interconnect delay = 2.380 ns ( 52.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.502 ns" { syn_count[7] Add0~354 Add0~350 Add0~352 Add0~332 Add0~334 Add0~369 syn_count[17] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.502 ns" { syn_count[7] Add0~354 Add0~350 Add0~352 Add0~332 Add0~334 Add0~369 syn_count[17] } { 0.000ns 1.149ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.231ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.208ns 0.679ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns syn_count\[17\] 2 REG LC_X12_Y16_N8 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y16_N8; Fanout = 5; REG Node = 'syn_count\[17\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk syn_count[17] } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_count[17] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_count[17] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns syn_count\[7\] 2 REG LC_X13_Y16_N9 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y16_N9; Fanout = 5; REG Node = 'syn_count\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk syn_count[7] } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_count[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_count[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_count[17] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_count[17] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_count[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_count[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.502 ns" { syn_count[7] Add0~354 Add0~350 Add0~352 Add0~332 Add0~334 Add0~369 syn_count[17] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.502 ns" { syn_count[7] Add0~354 Add0~350 Add0~352 Add0~332 Add0~334 Add0~369 syn_count[17] } { 0.000ns 1.149ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.231ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.208ns 0.679ns 0.478ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_count[17] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_count[17] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_count[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_count[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk syn_dm642 syn_dm642~reg0 7.696 ns register " "Info: tco from clock \"clk\" to destination pin \"syn_dm642\" through register \"syn_dm642~reg0\" is 7.696 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns syn_dm642~reg0 2 REG LC_X13_Y16_N4 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y16_N4; Fanout = 1; REG Node = 'syn_dm642~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk syn_dm642~reg0 } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_dm642~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_dm642~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.518 ns + Longest register pin " "Info: + Longest register to pin delay is 4.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns syn_dm642~reg0 1 REG LC_X13_Y16_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y16_N4; Fanout = 1; REG Node = 'syn_dm642~reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { syn_dm642~reg0 } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.394 ns) + CELL(2.124 ns) 4.518 ns syn_dm642 2 PIN PIN_15 0 " "Info: 2: + IC(2.394 ns) + CELL(2.124 ns) = 4.518 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'syn_dm642'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.518 ns" { syn_dm642~reg0 syn_dm642 } "NODE_NAME" } } { "DM642_syn.vhd" "" { Text "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 47.01 % ) " "Info: Total cell delay = 2.124 ns ( 47.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.394 ns ( 52.99 % ) " "Info: Total interconnect delay = 2.394 ns ( 52.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.518 ns" { syn_dm642~reg0 syn_dm642 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.518 ns" { syn_dm642~reg0 syn_dm642 } { 0.000ns 2.394ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk syn_dm642~reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 syn_dm642~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.518 ns" { syn_dm642~reg0 syn_dm642 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.518 ns" { syn_dm642~reg0 syn_dm642 } { 0.000ns 2.394ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 09 20:18:24 2009 " "Info: Processing ended: Thu Apr 09 20:18:24 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}