dm642_syn.vhd

来自「一个用vHDL语言编的同步程序」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity DM642_syn is
port(clk:in std_logic;
     syn_ir:out std_logic;
     syn_dm642:out std_logic 

);
end DM642_syn;

architecture rtl of DM642_syn is
signal syn_count:std_logic_vector(21 downto 0);
begin

process(clk)
begin
if(clk'event and clk='1') then
   if(syn_count=200000) then 
     syn_count<=(others=>'0'); 
   else
     syn_count<=syn_count+1;
   end if;
   if(syn_count<=40000) then 
      syn_ir<='1';
    else
      syn_ir<='0';
    end if;
    if(syn_count<81920+10 and syn_count>=10) then
      syn_dm642<='1';
    else
      syn_dm642<='0';
    end if;
end if;
end process;


end rtl;