📄 dm642_syn.sim.rpt
字号:
; |DM642_syn|Add0~359 ; |DM642_syn|Add0~360COUT1 ; cout1 ;
; |DM642_syn|Add0~367 ; |DM642_syn|Add0~367 ; combout ;
; |DM642_syn|Add0~369 ; |DM642_syn|Add0~369 ; combout ;
; |DM642_syn|Add0~369 ; |DM642_syn|Add0~370 ; cout0 ;
; |DM642_syn|syn_ir~reg0 ; |DM642_syn|syn_ir~reg0 ; regout ;
; |DM642_syn|syn_dm642~reg0 ; |DM642_syn|syn_dm642~reg0 ; regout ;
; |DM642_syn|syn_count[6] ; |DM642_syn|syn_count[6] ; regout ;
; |DM642_syn|syn_count[11] ; |DM642_syn|syn_count[11] ; regout ;
; |DM642_syn|syn_count[10] ; |DM642_syn|syn_count[10] ; regout ;
; |DM642_syn|syn_count[15] ; |DM642_syn|LessThan0~386 ; combout ;
; |DM642_syn|syn_count[15] ; |DM642_syn|syn_count[15] ; regout ;
; |DM642_syn|syn_count[3] ; |DM642_syn|syn_count[3] ; regout ;
; |DM642_syn|syn_count[0] ; |DM642_syn|syn_count[0] ; regout ;
; |DM642_syn|syn_count[1] ; |DM642_syn|Equal0~161 ; combout ;
; |DM642_syn|syn_count[1] ; |DM642_syn|syn_count[1] ; regout ;
; |DM642_syn|syn_count[4] ; |DM642_syn|syn_count[4] ; regout ;
; |DM642_syn|syn_count[5] ; |DM642_syn|Equal0~162 ; combout ;
; |DM642_syn|syn_count[5] ; |DM642_syn|syn_count[5] ; regout ;
; |DM642_syn|LessThan0~387 ; |DM642_syn|LessThan0~387 ; combout ;
; |DM642_syn|syn_count[8] ; |DM642_syn|syn_count[8] ; regout ;
; |DM642_syn|syn_count[9] ; |DM642_syn|LessThan0~388 ; combout ;
; |DM642_syn|syn_count[9] ; |DM642_syn|syn_count[9] ; regout ;
; |DM642_syn|syn_count[16] ; |DM642_syn|syn_count[16] ; regout ;
; |DM642_syn|syn_count[13] ; |DM642_syn|syn_count[13] ; regout ;
; |DM642_syn|syn_count[14] ; |DM642_syn|LessThan0~389 ; combout ;
; |DM642_syn|syn_count[14] ; |DM642_syn|syn_count[14] ; regout ;
; |DM642_syn|syn_count[17] ; |DM642_syn|syn_count[17] ; regout ;
; |DM642_syn|process0~237 ; |DM642_syn|process0~237 ; combout ;
; |DM642_syn|syn_count[12] ; |DM642_syn|Equal0~164 ; combout ;
; |DM642_syn|syn_count[12] ; |DM642_syn|syn_count[12] ; regout ;
; |DM642_syn|syn_count[2] ; |DM642_syn|LessThan1~277 ; combout ;
; |DM642_syn|syn_count[2] ; |DM642_syn|syn_count[2] ; regout ;
; |DM642_syn|process0~238 ; |DM642_syn|process0~238 ; combout ;
; |DM642_syn|process0~239 ; |DM642_syn|process0~239 ; combout ;
; |DM642_syn|Equal0~165 ; |DM642_syn|Equal0~165 ; combout ;
; |DM642_syn|Equal0~166 ; |DM642_syn|Equal0~166 ; combout ;
; |DM642_syn|Equal0~167 ; |DM642_syn|Equal0~167 ; combout ;
; |DM642_syn|syn_count[7] ; |DM642_syn|LessThan0~391 ; combout ;
; |DM642_syn|syn_count[7] ; |DM642_syn|syn_count[7] ; regout ;
; |DM642_syn|syn_ir ; |DM642_syn|syn_ir ; padio ;
; |DM642_syn|syn_dm642 ; |DM642_syn|syn_dm642 ; padio ;
; |DM642_syn|clk ; |DM642_syn|clk ; combout ;
+---------------------------+---------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------------+--------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------+--------------------------+------------------+
; |DM642_syn|Add0~327 ; |DM642_syn|Add0~328COUT1 ; cout1 ;
; |DM642_syn|Add0~329 ; |DM642_syn|Add0~330 ; cout0 ;
; |DM642_syn|Add0~335 ; |DM642_syn|Add0~336 ; cout0 ;
; |DM642_syn|Add0~337 ; |DM642_syn|Add0~338 ; cout0 ;
; |DM642_syn|Add0~339 ; |DM642_syn|Add0~340 ; cout0 ;
; |DM642_syn|Add0~341 ; |DM642_syn|Add0~342 ; cout0 ;
; |DM642_syn|Add0~347 ; |DM642_syn|Add0~348 ; cout0 ;
; |DM642_syn|Add0~349 ; |DM642_syn|Add0~350COUT1 ; cout1 ;
; |DM642_syn|Add0~351 ; |DM642_syn|Add0~352COUT1 ; cout1 ;
; |DM642_syn|Add0~353 ; |DM642_syn|Add0~354COUT1 ; cout1 ;
; |DM642_syn|Add0~355 ; |DM642_syn|Add0~356COUT1 ; cout1 ;
; |DM642_syn|Add0~357 ; |DM642_syn|Add0~358 ; cout0 ;
; |DM642_syn|Add0~359 ; |DM642_syn|Add0~360 ; cout0 ;
; |DM642_syn|Add0~361 ; |DM642_syn|Add0~361 ; combout ;
; |DM642_syn|Add0~363 ; |DM642_syn|Add0~363 ; combout ;
; |DM642_syn|Add0~363 ; |DM642_syn|Add0~364 ; cout ;
; |DM642_syn|Add0~365 ; |DM642_syn|Add0~365 ; combout ;
; |DM642_syn|Add0~365 ; |DM642_syn|Add0~366 ; cout0 ;
; |DM642_syn|Add0~365 ; |DM642_syn|Add0~366COUT1 ; cout1 ;
; |DM642_syn|Add0~367 ; |DM642_syn|Add0~368 ; cout0 ;
; |DM642_syn|Add0~367 ; |DM642_syn|Add0~368COUT1 ; cout1 ;
; |DM642_syn|Add0~369 ; |DM642_syn|Add0~370COUT1 ; cout1 ;
; |DM642_syn|syn_count[20] ; |DM642_syn|syn_count[20] ; regout ;
; |DM642_syn|syn_count[19] ; |DM642_syn|syn_count[19] ; regout ;
; |DM642_syn|syn_count[18] ; |DM642_syn|syn_count[18] ; regout ;
; |DM642_syn|syn_count[21] ; |DM642_syn|Equal0~163 ; combout ;
; |DM642_syn|syn_count[21] ; |DM642_syn|syn_count[21] ; regout ;
+--------------------------+--------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------+--------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------+--------------------------+------------------+
; |DM642_syn|Add0~327 ; |DM642_syn|Add0~328COUT1 ; cout1 ;
; |DM642_syn|Add0~329 ; |DM642_syn|Add0~330 ; cout0 ;
; |DM642_syn|Add0~335 ; |DM642_syn|Add0~336 ; cout0 ;
; |DM642_syn|Add0~337 ; |DM642_syn|Add0~338 ; cout0 ;
; |DM642_syn|Add0~339 ; |DM642_syn|Add0~340 ; cout0 ;
; |DM642_syn|Add0~341 ; |DM642_syn|Add0~342 ; cout0 ;
; |DM642_syn|Add0~347 ; |DM642_syn|Add0~348 ; cout0 ;
; |DM642_syn|Add0~349 ; |DM642_syn|Add0~350COUT1 ; cout1 ;
; |DM642_syn|Add0~351 ; |DM642_syn|Add0~352COUT1 ; cout1 ;
; |DM642_syn|Add0~353 ; |DM642_syn|Add0~354COUT1 ; cout1 ;
; |DM642_syn|Add0~355 ; |DM642_syn|Add0~356COUT1 ; cout1 ;
; |DM642_syn|Add0~357 ; |DM642_syn|Add0~358 ; cout0 ;
; |DM642_syn|Add0~359 ; |DM642_syn|Add0~360 ; cout0 ;
; |DM642_syn|Add0~361 ; |DM642_syn|Add0~361 ; combout ;
; |DM642_syn|Add0~363 ; |DM642_syn|Add0~363 ; combout ;
; |DM642_syn|Add0~363 ; |DM642_syn|Add0~364 ; cout ;
; |DM642_syn|Add0~365 ; |DM642_syn|Add0~365 ; combout ;
; |DM642_syn|Add0~365 ; |DM642_syn|Add0~366 ; cout0 ;
; |DM642_syn|Add0~365 ; |DM642_syn|Add0~366COUT1 ; cout1 ;
; |DM642_syn|Add0~367 ; |DM642_syn|Add0~368 ; cout0 ;
; |DM642_syn|Add0~367 ; |DM642_syn|Add0~368COUT1 ; cout1 ;
; |DM642_syn|Add0~369 ; |DM642_syn|Add0~370COUT1 ; cout1 ;
; |DM642_syn|syn_count[20] ; |DM642_syn|syn_count[20] ; regout ;
; |DM642_syn|syn_count[19] ; |DM642_syn|syn_count[19] ; regout ;
; |DM642_syn|syn_count[18] ; |DM642_syn|syn_count[18] ; regout ;
; |DM642_syn|syn_count[21] ; |DM642_syn|Equal0~163 ; combout ;
; |DM642_syn|syn_count[21] ; |DM642_syn|syn_count[21] ; regout ;
+--------------------------+--------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Thu Apr 09 20:34:17 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DM642_syn -c DM642_syn
Info: Using vector source file "C:/Users/mayajun/Desktop/EDA/DM642_syn/DM642_syn.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 73.53 %
Info: Number of transitions in simulation is 4711644
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 121 megabytes of memory during processing
Info: Processing ended: Thu Apr 09 20:36:27 2009
Info: Elapsed time: 00:02:10
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -